{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1621197102253 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1621197102253 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 16 23:31:42 2021 " "Processing started: Sun May 16 23:31:42 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1621197102253 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197102253 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197102253 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1621197102418 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1621197102418 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1621197109195 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197109195 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "dp DP seg7x8_dp.v(3) " "Verilog HDL Declaration information at seg7x8_dp.v(3): object \"dp\" differs only in case from object \"DP\" in the same scope" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 3 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1621197109195 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "output_files/seg7x8_dp.v 1 1 " "Found 1 design units, including 1 entities, in source file output_files/seg7x8_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 seg7x8_dp " "Found entity 1: seg7x8_dp" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1621197109196 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197109196 ""}
{ "Error" "EVRFX_VERI_MEMORY_ACCESS" "number top.v(11) " "Verilog HDL error at top.v(11): expression cannot reference entire array \"number\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 11 0 0 } }  } 0 10044 "Verilog HDL error at %2!s!: expression cannot reference entire array \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1621197109196 ""}
{ "Error" "EVRFX_VERI_MEMORY_ASSIGNMENT" "number top.v(37) " "Verilog HDL error at top.v(37): values cannot be assigned directly to all or part of array \"number\" - assignments must be made to individual elements only" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 37 0 0 } }  } 0 10048 "Verilog HDL error at %2!s!: values cannot be assigned directly to all or part of array \"%1!s!\" - assignments must be made to individual elements only" 0 0 "Analysis & Synthesis" 0 -1 1621197109196 ""}
{ "Error" "EVRFX_SV_1040_UNCONVERTED" "number top.v(37) " "SystemVerilog error at top.v(37): number has an aggregate value" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 37 0 0 } }  } 0 10686 "SystemVerilog error at %2!s!: %1!s! has an aggregate value" 0 0 "Analysis & Synthesis" 0 -1 1621197109196 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Peak virtual memory: 351 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1621197109237 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun May 16 23:31:49 2021 " "Processing ended: Sun May 16 23:31:49 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1621197109237 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1621197109237 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1621197109237 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197109237 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 1  " "Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197109398 ""}
