{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224927646 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224927646 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:07 2021 " "Processing started: Sat Apr 24 03:42:07 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224927646 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224927646 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224927647 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619224927824 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619224927824 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "../../../Ð Ð°Ð±Ð¾ÑÐ¸Ð¹ ÑÑÐ¾Ð»/a-c4e6e10_exemple/AHDL_test/template.bdf " "Can't analyze file -- file ../../../Ð Ð°Ð±Ð¾ÑÐ¸Ð¹ ÑÑÐ¾Ð»/a-c4e6e10_exemple/AHDL_test/template.bdf is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1619224934924 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.bdf 1 1 " "Found 1 design units, including 1 entities, in source file template.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 template " "Found entity 1: template" {  } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934926 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934926 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 7 " "Group MSB D7 overrides BIT0 = LSB in actual or default Options Statement" {  } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } }  } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 3 " "Group MSB D3 overrides BIT0 = LSB in actual or default Options Statement" {  } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } }  } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "dig 7 " "Group MSB dig7 overrides BIT0 = LSB in actual or default Options Statement" {  } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 5 5 0 } }  } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""}
{ "Warning" "WTDFX_RANGE_CONFLICT" "D 7 0 D 0 7 " "Group is used as \"D\[7..0\]\" and defined using a different range order (\"D\[0..7\]\")" {  } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } }  } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""}
{ "Warning" "WTDFX_RANGE_CONFLICT" "D 3 0 D 0 3 " "Group is used as \"D\[3..0\]\" and defined using a different range order (\"D\[0..3\]\")" {  } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } }  } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "decoder_out " "Variable or input pin \"decoder_out\" is defined but never used." {  } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 10 16 0 } }  } 0 287013 "Variable or input pin \"%1!s!\" is defined but never used." 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.tdf 1 1 " "Found 1 design units, including 1 entities, in source file template.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 LED_7seg_driver " "Found entity 1: LED_7seg_driver" {  } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 3 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934930 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "7seg_driver.tdf 1 1 " "Found 1 design units, including 1 entities, in source file 7seg_driver.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7seg_driver " "Found entity 1: 7seg_driver" {  } { { "7seg_driver.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/7seg_driver.tdf" 1 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934931 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934931 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.tdf 1 1 " "Found 1 design units, including 1 entities, in source file test.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Found entity 1: test" {  } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 1 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934931 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934931 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "template " "Elaborating entity \"template\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619224934975 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_7seg_driver LED_7seg_driver:inst " "Elaborating entity \"LED_7seg_driver\" for hierarchy \"LED_7seg_driver:inst\"" {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934978 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7seg_driver LED_7seg_driver:inst\|7seg_driver:\$00000 " "Elaborating entity \"7seg_driver\" for hierarchy \"LED_7seg_driver:inst\|7seg_driver:\$00000\"" {  } { { "template.tdf" "\$00000" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 31 31 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934982 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "test test:inst4 " "Elaborating entity \"test\" for hierarchy \"test:inst4\"" {  } { { "template.bdf" "inst4" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 200 64 248 280 "inst4" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934986 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[0\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[0\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\".  The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\".  The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[1\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[1\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\".  The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\".  The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[2\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[2\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\".  The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\".  The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[3\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[3\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\".  The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\".  The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[4\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[4\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\".  The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\".  The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[5\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[5\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\".  The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\".  The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[6\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[6\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\".  The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\".  The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[7\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[7\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\".  The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." {  } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } }  } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\".  The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[0\] GND " "Pin \"HEX\[0\]\" is stuck at GND" {  } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[1\] GND " "Pin \"HEX\[1\]\" is stuck at GND" {  } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[2\] GND " "Pin \"HEX\[2\]\" is stuck at GND" {  } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[3\] GND " "Pin \"HEX\[3\]\" is stuck at GND" {  } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[4\] GND " "Pin \"HEX\[4\]\" is stuck at GND" {  } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[4]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1619224935469 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619224935558 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1619224936053 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224936053 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1619224936080 ""} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Implemented 15 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1619224936080 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1619224936080 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1619224936080 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 22 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:16 2021 " "Processing ended: Sat Apr 24 03:42:16 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224936087 ""}
