{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1621197158861 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1621197158861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 16 23:32:38 2021 " "Processing started: Sun May 16 23:32:38 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1621197158861 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197158861 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197158861 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1621197159034 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1621197159034 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1621197165758 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197165758 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "dp DP seg7x8_dp.v(3) " "Verilog HDL Declaration information at seg7x8_dp.v(3): object \"dp\" differs only in case from object \"DP\" in the same scope" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 3 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1621197165759 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "output_files/seg7x8_dp.v 1 1 " "Found 1 design units, including 1 entities, in source file output_files/seg7x8_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 seg7x8_dp " "Found entity 1: seg7x8_dp" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1621197165759 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197165759 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1621197165800 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg7x8_dp seg7x8_dp:my " "Elaborating entity \"seg7x8_dp\" for hierarchy \"seg7x8_dp:my\"" {  } { { "top.v" "my" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1621197165810 ""}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "seg7x8_dp.v(54) " "Verilog HDL Case Statement information at seg7x8_dp.v(54): all case item expressions in this case statement are onehot" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 54 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1621197165811 "|top|seg7x8_dp:my"}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "seg7x8_dp.v(66) " "Verilog HDL Case Statement information at seg7x8_dp.v(66): all case item expressions in this case statement are onehot" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 66 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1621197165811 "|top|seg7x8_dp:my"}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX_S\[7\] VCC " "Pin \"HEX_S\[7\]\" is stuck at VCC" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1621197166353 "|top|HEX_S[7]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1621197166353 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1621197166444 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1621197167075 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1621197167075 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "No output dependent on input pin \"SW\[5\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "No output dependent on input pin \"SW\[6\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "No output dependent on input pin \"SW\[7\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[8]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1621197167112 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "233 " "Implemented 233 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1621197167112 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1621197167112 ""} { "Info" "ICUT_CUT_TM_LCELLS" "196 " "Implemented 196 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1621197167112 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1621197167112 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/template.map.smsg " "Generated suppressed messages file /home/zen/tmp/a-c4e6e10_exemple/template/output_files/template.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197167118 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1621197167121 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 16 23:32:47 2021 " "Processing ended: Sun May 16 23:32:47 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1621197167121 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1621197167121 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1621197167121 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197167121 ""}
