add counter

counter_test/db/prev_cmp_template.qmsg

@@ -0,0 +1,13 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1621197102253 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1621197102253 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 16 23:31:42 2021 " "Processing started: Sun May 16 23:31:42 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1621197102253 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197102253 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197102253 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1621197102418 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1621197102418 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1621197109195 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197109195 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "dp DP seg7x8_dp.v(3) " "Verilog HDL Declaration information at seg7x8_dp.v(3): object \"dp\" differs only in case from object \"DP\" in the same scope" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 3 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1621197109195 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "output_files/seg7x8_dp.v 1 1 " "Found 1 design units, including 1 entities, in source file output_files/seg7x8_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 seg7x8_dp " "Found entity 1: seg7x8_dp" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1621197109196 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197109196 ""}
+{ "Error" "EVRFX_VERI_MEMORY_ACCESS" "number top.v(11) " "Verilog HDL error at top.v(11): expression cannot reference entire array \"number\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 11 0 0 } }  } 0 10044 "Verilog HDL error at %2!s!: expression cannot reference entire array \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1621197109196 ""}
+{ "Error" "EVRFX_VERI_MEMORY_ASSIGNMENT" "number top.v(37) " "Verilog HDL error at top.v(37): values cannot be assigned directly to all or part of array \"number\" - assignments must be made to individual elements only" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 37 0 0 } }  } 0 10048 "Verilog HDL error at %2!s!: values cannot be assigned directly to all or part of array \"%1!s!\" - assignments must be made to individual elements only" 0 0 "Analysis & Synthesis" 0 -1 1621197109196 ""}
+{ "Error" "EVRFX_SV_1040_UNCONVERTED" "number top.v(37) " "SystemVerilog error at top.v(37): number has an aggregate value" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 37 0 0 } }  } 0 10686 "SystemVerilog error at %2!s!: %1!s! has an aggregate value" 0 0 "Analysis & Synthesis" 0 -1 1621197109196 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Peak virtual memory: 351 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1621197109237 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun May 16 23:31:49 2021 " "Processing ended: Sun May 16 23:31:49 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1621197109237 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1621197109237 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1621197109237 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197109237 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 1  " "Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197109398 ""}

counter_test/db/template.asm.qmsg

@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1621197173389 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1621197173390 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 16 23:32:53 2021 " "Processing started: Sun May 16 23:32:53 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1621197173390 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1621197173390 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off template -c template " "Command: quartus_asm --read_settings_files=off --write_settings_files=off template -c template" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1621197173390 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1621197173572 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1621197173839 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1621197173850 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Peak virtual memory: 351 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1621197173923 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 16 23:32:53 2021 " "Processing ended: Sun May 16 23:32:53 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1621197173923 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1621197173923 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1621197173923 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1621197173923 ""}

counter_test/db/template.cbx.xml

@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="template">
+	</PROJECT>
+</LOG_ROOT>

counter_test/db/template.cmp.logdb

@@ -0,0 +1,79 @@
+v1
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;37;37;0;0;37;37;0;0;0;0;0;0;28;0;0;0;9;28;0;9;0;0;28;0;37;37;37;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,37;0;0;37;37;0;0;37;37;37;37;37;37;9;37;37;37;28;9;37;28;37;37;9;37;0;0;0;37;37,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[10],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[11],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[12],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[13],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[14],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX_S[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX_S[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX_S[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX_S[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX_S[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX_S[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX_S[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX_S[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLK_50M,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,

counter_test/db/template.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+Version_Index = 520278016
+Creation_Time = Mon May 17 01:56:59 2021

counter_test/db/template.hier_info

@@ -0,0 +1,165 @@
+|top
+SW[1] => ~NO_FANOUT~
+SW[2] => ~NO_FANOUT~
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => ~NO_FANOUT~
+SW[8] => ~NO_FANOUT~
+CLK_50M => seg7x8_dp:my.CLK
+CLK_50M => y.CLK
+CLK_50M => i[0].CLK
+CLK_50M => i[1].CLK
+CLK_50M => i[2].CLK
+CLK_50M => i[3].CLK
+CLK_50M => i[4].CLK
+CLK_50M => i[5].CLK
+CLK_50M => i[6].CLK
+CLK_50M => i[7].CLK
+CLK_50M => i[8].CLK
+CLK_50M => i[9].CLK
+CLK_50M => i[10].CLK
+CLK_50M => i[11].CLK
+CLK_50M => i[12].CLK
+CLK_50M => i[13].CLK
+CLK_50M => i[14].CLK
+CLK_50M => i[15].CLK
+CLK_50M => i[16].CLK
+CLK_50M => i[17].CLK
+CLK_50M => i[18].CLK
+CLK_50M => i[19].CLK
+CLK_50M => i[20].CLK
+CLK_50M => i[21].CLK
+CLK_50M => i[22].CLK
+CLK_50M => i[23].CLK
+CLK_50M => i[24].CLK
+CLK_50M => i[25].CLK
+CLK_50M => i[26].CLK
+CLK_50M => i[27].CLK
+CLK_50M => i[28].CLK
+CLK_50M => i[29].CLK
+CLK_50M => i[30].CLK
+CLK_50M => i[31].CLK
+D[3] <= j[0].DB_MAX_OUTPUT_PORT_TYPE
+D[4] <= j[1].DB_MAX_OUTPUT_PORT_TYPE
+D[5] <= j[2].DB_MAX_OUTPUT_PORT_TYPE
+D[6] <= j[3].DB_MAX_OUTPUT_PORT_TYPE
+D[7] <= j[4].DB_MAX_OUTPUT_PORT_TYPE
+D[8] <= j[5].DB_MAX_OUTPUT_PORT_TYPE
+D[9] <= j[6].DB_MAX_OUTPUT_PORT_TYPE
+D[10] <= j[7].DB_MAX_OUTPUT_PORT_TYPE
+D[11] <= j[8].DB_MAX_OUTPUT_PORT_TYPE
+D[12] <= j[9].DB_MAX_OUTPUT_PORT_TYPE
+D[13] <= j[10].DB_MAX_OUTPUT_PORT_TYPE
+D[14] <= j[11].DB_MAX_OUTPUT_PORT_TYPE
+HEX[0] <= seg7x8_dp:my.HEX[0]
+HEX[1] <= seg7x8_dp:my.HEX[1]
+HEX[2] <= seg7x8_dp:my.HEX[2]
+HEX[3] <= seg7x8_dp:my.HEX[3]
+HEX[4] <= seg7x8_dp:my.HEX[4]
+HEX[5] <= seg7x8_dp:my.HEX[5]
+HEX[6] <= seg7x8_dp:my.HEX[6]
+HEX[7] <= seg7x8_dp:my.HEX[7]
+HEX_S[7] <= seg7x8_dp:my.HEX_S[7]
+HEX_S[6] <= seg7x8_dp:my.HEX_S[6]
+HEX_S[5] <= seg7x8_dp:my.HEX_S[5]
+HEX_S[4] <= seg7x8_dp:my.HEX_S[4]
+HEX_S[3] <= seg7x8_dp:my.HEX_S[3]
+HEX_S[2] <= seg7x8_dp:my.HEX_S[2]
+HEX_S[1] <= seg7x8_dp:my.HEX_S[1]
+HEX_S[0] <= seg7x8_dp:my.HEX_S[0]
+
+
+|top|seg7x8_dp:my
+num[0] => Selector3.IN16
+num[1] => Selector2.IN16
+num[2] => Selector1.IN16
+num[3] => Selector0.IN16
+num[4] => Selector3.IN15
+num[5] => Selector2.IN15
+num[6] => Selector1.IN15
+num[7] => Selector0.IN15
+num[8] => Selector3.IN14
+num[9] => Selector2.IN14
+num[10] => Selector1.IN14
+num[11] => Selector0.IN14
+num[12] => Selector3.IN13
+num[13] => Selector2.IN13
+num[14] => Selector1.IN13
+num[15] => Selector0.IN13
+num[16] => Selector3.IN12
+num[17] => Selector2.IN12
+num[18] => Selector1.IN12
+num[19] => Selector0.IN12
+num[20] => Selector3.IN11
+num[21] => Selector2.IN11
+num[22] => Selector1.IN11
+num[23] => Selector0.IN11
+num[24] => Selector3.IN10
+num[25] => Selector2.IN10
+num[26] => Selector1.IN10
+num[27] => Selector0.IN10
+num[28] => Selector3.IN9
+num[29] => Selector2.IN9
+num[30] => Selector1.IN9
+num[31] => Selector0.IN9
+dp[0] => Selector4.IN16
+dp[1] => Selector4.IN15
+dp[2] => Selector4.IN14
+dp[3] => Selector4.IN13
+dp[4] => Selector4.IN12
+dp[5] => Selector4.IN11
+dp[6] => Selector4.IN10
+dp[7] => Selector4.IN9
+CLK => y.CLK
+CLK => i[0].CLK
+CLK => i[1].CLK
+CLK => i[2].CLK
+CLK => i[3].CLK
+CLK => i[4].CLK
+CLK => i[5].CLK
+CLK => i[6].CLK
+CLK => i[7].CLK
+CLK => i[8].CLK
+CLK => i[9].CLK
+CLK => i[10].CLK
+CLK => i[11].CLK
+CLK => i[12].CLK
+CLK => i[13].CLK
+CLK => i[14].CLK
+CLK => i[15].CLK
+CLK => i[16].CLK
+CLK => i[17].CLK
+CLK => i[18].CLK
+CLK => i[19].CLK
+CLK => i[20].CLK
+CLK => i[21].CLK
+CLK => i[22].CLK
+CLK => i[23].CLK
+CLK => i[24].CLK
+CLK => i[25].CLK
+CLK => i[26].CLK
+CLK => i[27].CLK
+CLK => i[28].CLK
+CLK => i[29].CLK
+CLK => i[30].CLK
+CLK => i[31].CLK
+HEX[0] <= j[0].DB_MAX_OUTPUT_PORT_TYPE
+HEX[1] <= j[1].DB_MAX_OUTPUT_PORT_TYPE
+HEX[2] <= j[2].DB_MAX_OUTPUT_PORT_TYPE
+HEX[3] <= j[3].DB_MAX_OUTPUT_PORT_TYPE
+HEX[4] <= j[4].DB_MAX_OUTPUT_PORT_TYPE
+HEX[5] <= j[5].DB_MAX_OUTPUT_PORT_TYPE
+HEX[6] <= j[6].DB_MAX_OUTPUT_PORT_TYPE
+HEX[7] <= j[7].DB_MAX_OUTPUT_PORT_TYPE
+HEX_S[7] <= DP.DB_MAX_OUTPUT_PORT_TYPE
+HEX_S[6] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+HEX_S[5] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+HEX_S[4] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+HEX_S[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+HEX_S[2] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+HEX_S[1] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+HEX_S[0] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+

counter_test/db/template.lpc.html

@@ -0,0 +1,34 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >my</TD>
+<TD >41</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >16</TD>
+<TD >8</TD>
+<TD >8</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>

counter_test/db/template.lpc.txt

@@ -0,0 +1,7 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; my        ; 41    ; 8              ; 0            ; 8              ; 16     ; 8               ; 8             ; 8               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

counter_test/db/template.map.logdb

@@ -0,0 +1 @@
+v1

counter_test/db/template.map.qmsg

@@ -0,0 +1,19 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1621197158861 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1621197158861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 16 23:32:38 2021 " "Processing started: Sun May 16 23:32:38 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1621197158861 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197158861 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197158861 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1621197159034 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1621197159034 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1621197165758 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197165758 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "dp DP seg7x8_dp.v(3) " "Verilog HDL Declaration information at seg7x8_dp.v(3): object \"dp\" differs only in case from object \"DP\" in the same scope" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 3 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1621197165759 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "output_files/seg7x8_dp.v 1 1 " "Found 1 design units, including 1 entities, in source file output_files/seg7x8_dp.v" { { "Info" "ISGN_ENTITY_NAME" "1 seg7x8_dp " "Found entity 1: seg7x8_dp" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1621197165759 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197165759 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1621197165800 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg7x8_dp seg7x8_dp:my " "Elaborating entity \"seg7x8_dp\" for hierarchy \"seg7x8_dp:my\"" {  } { { "top.v" "my" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1621197165810 ""}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "seg7x8_dp.v(54) " "Verilog HDL Case Statement information at seg7x8_dp.v(54): all case item expressions in this case statement are onehot" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 54 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1621197165811 "|top|seg7x8_dp:my"}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "seg7x8_dp.v(66) " "Verilog HDL Case Statement information at seg7x8_dp.v(66): all case item expressions in this case statement are onehot" {  } { { "output_files/seg7x8_dp.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v" 66 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1621197165811 "|top|seg7x8_dp:my"}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX_S\[7\] VCC " "Pin \"HEX_S\[7\]\" is stuck at VCC" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1621197166353 "|top|HEX_S[7]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1621197166353 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1621197166444 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1621197167075 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1621197167075 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "No output dependent on input pin \"SW\[5\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "No output dependent on input pin \"SW\[6\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "No output dependent on input pin \"SW\[7\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "top.v" "" { Text "/home/zen/tmp/a-c4e6e10_exemple/template/top.v" 2 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1621197167112 "|top|SW[8]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1621197167112 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "233 " "Implemented 233 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Implemented 9 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1621197167112 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1621197167112 ""} { "Info" "ICUT_CUT_TM_LCELLS" "196 " "Implemented 196 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1621197167112 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1621197167112 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/zen/tmp/a-c4e6e10_exemple/template/output_files/template.map.smsg " "Generated suppressed messages file /home/zen/tmp/a-c4e6e10_exemple/template/output_files/template.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197167118 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1621197167121 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 16 23:32:47 2021 " "Processing ended: Sun May 16 23:32:47 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1621197167121 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1621197167121 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1621197167121 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1621197167121 ""}

counter_test/db/template.map_bb.logdb

@@ -0,0 +1 @@
+v1

counter_test/db/template.smart_action.txt

@@ -0,0 +1 @@
+DONE

counter_test/db/template.sta.qmsg

@@ -0,0 +1,42 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1621197174732 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1621197174732 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 16 23:32:54 2021 " "Processing started: Sun May 16 23:32:54 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1621197174732 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1621197174732 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta template -c template " "Command: quartus_sta template -c template" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1621197174732 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1621197174768 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1621197174840 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1621197174840 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197174911 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197174911 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "template.sdc " "Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1621197175094 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175094 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name y y " "create_clock -period 1.000 -name y y" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1621197175096 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK_50M CLK_50M " "create_clock -period 1.000 -name CLK_50M CLK_50M" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1621197175096 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name seg7x8_dp:my\|y seg7x8_dp:my\|y " "create_clock -period 1.000 -name seg7x8_dp:my\|y seg7x8_dp:my\|y" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1621197175096 ""}  } {  } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1621197175096 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1621197175098 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1621197175099 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1621197175099 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1621197175105 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1621197175125 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1621197175125 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.547 " "Worst-case setup slack is -3.547" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.547            -155.487 CLK_50M  " "   -3.547            -155.487 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.088             -17.556 seg7x8_dp:my\|y  " "   -3.088             -17.556 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.899             -67.661 y  " "   -2.899             -67.661 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175126 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175126 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.516 " "Worst-case hold slack is 0.516" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175128 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175128 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.516               0.000 y  " "    0.516               0.000 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175128 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.634               0.000 CLK_50M  " "    0.634               0.000 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175128 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.738               0.000 seg7x8_dp:my\|y  " "    0.738               0.000 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175128 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175128 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1621197175128 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1621197175129 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000            -101.142 CLK_50M  " "   -3.000            -101.142 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -65.428 y  " "   -1.487             -65.428 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -17.844 seg7x8_dp:my\|y  " "   -1.487             -17.844 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175130 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175130 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1621197175166 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1621197175187 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1621197175405 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1621197175456 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1621197175460 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1621197175460 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.201 " "Worst-case setup slack is -3.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175462 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175462 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.201            -133.733 CLK_50M  " "   -3.201            -133.733 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175462 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.838             -15.657 seg7x8_dp:my\|y  " "   -2.838             -15.657 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175462 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.490             -57.440 y  " "   -2.490             -57.440 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175462 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175462 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.477 " "Worst-case hold slack is 0.477" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.477               0.000 y  " "    0.477               0.000 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.566               0.000 CLK_50M  " "    0.566               0.000 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.676               0.000 seg7x8_dp:my\|y  " "    0.676               0.000 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175465 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175465 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1621197175467 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1621197175469 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175471 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175471 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000            -101.142 CLK_50M  " "   -3.000            -101.142 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175471 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -65.428 y  " "   -1.487             -65.428 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175471 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487             -17.844 seg7x8_dp:my\|y  " "   -1.487             -17.844 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175471 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175471 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1621197175516 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1621197175614 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1621197175616 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1621197175616 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.883 " "Worst-case setup slack is -0.883" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175619 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175619 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.883             -30.950 CLK_50M  " "   -0.883             -30.950 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175619 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.793              -3.418 seg7x8_dp:my\|y  " "   -0.793              -3.418 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175619 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.741             -10.730 y  " "   -0.741             -10.730 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175619 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175619 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.210 " "Worst-case hold slack is 0.210" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.210               0.000 y  " "    0.210               0.000 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.265               0.000 CLK_50M  " "    0.265               0.000 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.287               0.000 seg7x8_dp:my\|y  " "    0.287               0.000 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175623 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175623 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1621197175626 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1621197175628 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -73.376 CLK_50M  " "   -3.000             -73.376 CLK_50M " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -44.000 y  " "   -1.000             -44.000 y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -12.000 seg7x8_dp:my\|y  " "   -1.000             -12.000 seg7x8_dp:my\|y " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1621197175631 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1621197175631 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1621197176029 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1621197176029 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "449 " "Peak virtual memory: 449 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1621197176072 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 16 23:32:56 2021 " "Processing ended: Sun May 16 23:32:56 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1621197176072 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1621197176072 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1621197176072 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1621197176072 ""}

counter_test/db/template.tmw_info

@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:19
+start_analysis_synthesis:s:00:00:10-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:05-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation

counter_test/db/template_partition_pins.json

@@ -0,0 +1,121 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "D[3]",
+					"strict" : false
+				},
+				{
+					"name" : "D[4]",
+					"strict" : false
+				},
+				{
+					"name" : "D[5]",
+					"strict" : false
+				},
+				{
+					"name" : "D[6]",
+					"strict" : false
+				},
+				{
+					"name" : "D[7]",
+					"strict" : false
+				},
+				{
+					"name" : "D[8]",
+					"strict" : false
+				},
+				{
+					"name" : "D[9]",
+					"strict" : false
+				},
+				{
+					"name" : "D[10]",
+					"strict" : false
+				},
+				{
+					"name" : "D[11]",
+					"strict" : false
+				},
+				{
+					"name" : "D[12]",
+					"strict" : false
+				},
+				{
+					"name" : "D[13]",
+					"strict" : false
+				},
+				{
+					"name" : "D[14]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX[7]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX_S[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX_S[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX_S[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX_S[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX_S[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX_S[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX_S[0]",
+					"strict" : false
+				},
+				{
+					"name" : "CLK_50M",
+					"strict" : false
+				}
+			]
+		}
+	]
+}

counter_test/incremental_db/README

@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+

counter_test/incremental_db/compiled_partitions/template.db_info

@@ -0,0 +1,3 @@
+Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+Version_Index = 520278016
+Creation_Time = Sat May 15 19:49:57 2021

counter_test/incremental_db/compiled_partitions/template.root_partition.cmp.logdb

@@ -0,0 +1 @@
+v1

counter_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.sig

@@ -0,0 +1 @@
+c5eb7f6cdd530884c3b884e0a3668ea4

counter_test/output_files/seg7x8_dp.v

@@ -0,0 +1,80 @@
+module seg7x8_dp(
+  input [31:0]num,
+  input [7:0] dp,
+  input CLK,
+  output [7:0] HEX,
+  output [0:7] HEX_S
+);
+   reg y;
+	reg [31:0] i;
+	always @(posedge CLK)
+	begin
+		i<=i+1;
+		if (i == 10_000) 
+		begin
+			y <= 1; 
+			i <= 0;
+		end
+		else y <= 0; 
+	end
+	
+	reg [6:0] h;
+	reg [3:0] n;
+	always @(*)
+	begin
+		case (n)			//ABCD_EFG
+			4'h0 : h = 7'b1111_110;
+			4'h1 : h = 7'b0110_000;
+			4'h2 : h = 7'b1101_101;
+			4'h3 : h = 7'b1111_001;
+			4'h4 : h = 7'b0110_011;
+			4'h5 : h = 7'b1011_011;
+			4'h6 : h = 7'b1011_111;
+			4'h7 : h = 7'b1110_000;
+			4'h8 : h = 7'b1111_111;
+			4'h9 : h = 7'b1111_011;
+			4'hA : h = 7'b1110_111;
+			4'hB : h = 7'b0011_111;
+			4'hC : h = 7'b1001_110;
+			4'hD : h = 7'b0111_101;
+			4'hE : h = 7'b1001_111;
+			4'hF : h = 7'b1000_111;
+		endcase
+	end
+	
+	reg DP = 0;
+	assign HEX_S = {~h[6:0],~DP};
+	
+	reg [7:0]j=8'b0000_0001;
+	always @(posedge y)
+	begin
+		j<=j<<1;
+		if (j == 8'b1000_0000) j <= 8'b0000_0001;
+		
+		case (j)
+			8'b1000_0000 : n <= num[3:0];
+			8'b0100_0000 : n <= num[31:28];
+			8'b0010_0000 : n <= num[27:24];
+			8'b0001_0000 : n <= num[23:20];
+			
+			8'b0000_1000 : n <= num[19:16];
+			8'b0000_0100 : n <= num[15:12];
+			8'b0000_0010 : n <= num[11:8];
+			8'b0000_0001 : n <= num[7:4];
+		endcase
+		
+		case (j)
+			8'b1000_0000 : DP <= dp[0];
+			8'b0100_0000 : DP <= dp[1];
+			8'b0010_0000 : DP <= dp[2];
+			8'b0001_0000 : DP <= dp[3];
+			
+			8'b0000_1000 : DP <= dp[4];
+			8'b0000_0100 : DP <= dp[5];
+			8'b0000_0010 : DP <= dp[6];
+			8'b0000_0001 : DP <= dp[7];
+		endcase
+	end
+	assign HEX = ~ j;
+	
+endmodule

counter_test/output_files/seg7x8_dp.v.bak

@@ -0,0 +1,65 @@
+module seg7x8_dp(
+  input [3:0][7:0]num,
+  input [7:0] dp;
+  input CLK,
+  output [7:0] HEX,
+  output [0:7] HEX_S
+);
+   reg y;
+	reg [31:0] i;
+	always @(posedge CLK)
+	begin
+		i<=i+1;
+		if (i == 1_000_000) 
+		begin
+			y <= 1; 
+			i <= 0;
+		end
+		else y <= 0; 
+	end
+	
+	reg [6:0] h;
+	reg [3:0] n;
+	always @(*)
+	begin
+		case (n)			//ABCD_EFG
+			4'h1 : h = 8'b0110_000;
+			4'h2 : h = 8'b1101_101;
+			4'h3 : h = 8'b1111_001;
+			4'h4 : h = 8'b0111_100;
+			4'h5 : h = 8'b1011_011;
+			4'h6 : h = 8'b1011_111;
+			4'h7 : h = 8'b1110_000;
+			4'h8 : h = 8'b1111_111;
+			4'h9 : h = 8'b1111_011;
+			4'hA : h = 8'b1110_111;
+			4'hB : h = 8'b0011_111;
+			4'hC : h = 8'b1001_110;
+			4'hD : h = 8'b0111_110;
+			4'hE : h = 8'b1001_111;
+			4'hF : h = 8'b0001_111;
+	end
+	
+	assign HEX_S = {h[6:0],1'b1}
+	
+	reg [7:0]j=8'b0000_0001;
+	always @(posedge y)
+	begin
+		j<=j<<1;
+		if (j == 8'b1000_0000) j <= 8'b0000_0001;
+		
+		case (j)
+			0b'b0000_0001 : n = num[0];
+			0b'b0000_0010 : n = num[1];
+			0b'b0000_0100 : n = num[2];
+			0b'b0000_1000 : n = num[3];
+			0b'b0001_0000 : n = num[4];
+			0b'b0010_0000 : n = num[5];
+			0b'b0100_0000 : n = num[6];
+			0b'b1000_0000 : n = num[6];
+	end
+	assign HEX = ~ j;
+	
+
+  assign HEX_S = ~ 8'b0111_1100;
+endmodule

counter_test/output_files/template.asm.rpt

@@ -0,0 +1,92 @@
+Assembler report for template
+Sun May 16 23:32:53 2021
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: template.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Sun May 16 23:32:53 2021 ;
+; Revision Name         ; template                              ;
+; Top-level Entity Name ; top                                   ;
+; Family                ; Cyclone IV E                          ;
+; Device                ; EP4CE10E22C8                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++--------------------------------------------------------------------+
+; Assembler Generated Files                                          ;
++--------------------------------------------------------------------+
+; File Name                                                          ;
++--------------------------------------------------------------------+
+; /home/zen/tmp/a-c4e6e10_exemple/template/output_files/template.sof ;
++--------------------------------------------------------------------+
+
+
++----------------------------------------+
+; Assembler Device Options: template.sof ;
++----------------+-----------------------+
+; Option         ; Setting               ;
++----------------+-----------------------+
+; JTAG usercode  ; 0x000AB69D            ;
+; Checksum       ; 0x000AB69D            ;
++----------------+-----------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+    Info: Processing started: Sun May 16 23:32:53 2021
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off template -c template
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 351 megabytes
+    Info: Processing ended: Sun May 16 23:32:53 2021
+    Info: Elapsed time: 00:00:00
+    Info: Total CPU time (on all processors): 00:00:01
+
+

counter_test/output_files/template.cdf

@@ -0,0 +1,13 @@
+/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP4CE10E22) Path("/home/zen/tmp/a-c4e6e10_exemple/template/output_files/") File("template.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;

counter_test/output_files/template.done

@@ -0,0 +1 @@
+Sun May 16 23:32:56 2021

counter_test/output_files/template.fit.smsg

@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

counter_test/output_files/template.fit.summary

@@ -0,0 +1,16 @@
+Fitter Status : Successful - Sun May 16 23:32:52 2021
+Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+Revision Name : template
+Top-level Entity Name : top
+Family : Cyclone IV E
+Device : EP4CE10E22C8
+Timing Models : Final
+Total logic elements : 190 / 10,320 ( 2 % )
+    Total combinational functions : 178 / 10,320 ( 2 % )
+    Dedicated logic registers : 122 / 10,320 ( 1 % )
+Total registers : 122
+Total pins : 37 / 92 ( 40 % )
+Total virtual pins : 0
+Total memory bits : 0 / 423,936 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % )
+Total PLLs : 0 / 2 ( 0 % )

counter_test/output_files/template.flow.rpt

@@ -0,0 +1,125 @@
+Flow report for template
+Sun May 16 23:32:56 2021
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++------------------------------------+---------------------------------------------+
+; Flow Status                        ; Successful - Sun May 16 23:32:53 2021       ;
+; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
+; Revision Name                      ; template                                    ;
+; Top-level Entity Name              ; top                                         ;
+; Family                             ; Cyclone IV E                                ;
+; Device                             ; EP4CE10E22C8                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 190 / 10,320 ( 2 % )                        ;
+;     Total combinational functions  ; 178 / 10,320 ( 2 % )                        ;
+;     Dedicated logic registers      ; 122 / 10,320 ( 1 % )                        ;
+; Total registers                    ; 122                                         ;
+; Total pins                         ; 37 / 92 ( 40 % )                            ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 0 / 423,936 ( 0 % )                         ;
+; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 2 ( 0 % )                               ;
++------------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 05/16/2021 23:32:38 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; template            ;
++-------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                        ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 79871138160810.162119715852397         ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                   ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; top         ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; top         ; Top        ;
+; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; top         ; Top        ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --         ;
+; TOP_LEVEL_ENTITY                    ; top                                    ; template      ; --          ; --         ;
++-------------------------------------+----------------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:08     ; 1.0                     ; 426 MB              ; 00:00:21                           ;
+; Fitter               ; 00:00:05     ; 1.0                     ; 970 MB              ; 00:00:06                           ;
+; Assembler            ; 00:00:00     ; 1.0                     ; 351 MB              ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 449 MB              ; 00:00:02                           ;
+; Total                ; 00:00:15     ; --                      ; --                  ; 00:00:30                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++----------------------+------------------+----------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name        ; OS Version ; Processor type ;
++----------------------+------------------+----------------+------------+----------------+
+; Analysis & Synthesis ; AW17R3           ; Ubuntu 20.04.2 ; 20         ; x86_64         ;
+; Fitter               ; AW17R3           ; Ubuntu 20.04.2 ; 20         ; x86_64         ;
+; Assembler            ; AW17R3           ; Ubuntu 20.04.2 ; 20         ; x86_64         ;
+; Timing Analyzer      ; AW17R3           ; Ubuntu 20.04.2 ; 20         ; x86_64         ;
++----------------------+------------------+----------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off template -c template
+quartus_fit --read_settings_files=off --write_settings_files=off template -c template
+quartus_asm --read_settings_files=off --write_settings_files=off template -c template
+quartus_sta template -c template
+
+
+

counter_test/output_files/template.jdi

@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="34462363bb5b29ef11f2"/>
+  </project>
+  <file_info>
+    <file device="EP4CE10E22C8" path="template.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>

counter_test/output_files/template.map.rpt

@@ -0,0 +1,362 @@
+Analysis & Synthesis report for template
+Sun May 16 23:32:47 2021
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Registers Removed During Synthesis
+  9. General Register Statistics
+ 10. Inverted Register Statistics
+ 11. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 12. Port Connectivity Checks: "seg7x8_dp:my"
+ 13. Post-Synthesis Netlist Statistics for Top Partition
+ 14. Elapsed Time Per Partition
+ 15. Analysis & Synthesis Messages
+ 16. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++------------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Sun May 16 23:32:47 2021       ;
+; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
+; Revision Name                      ; template                                    ;
+; Top-level Entity Name              ; top                                         ;
+; Family                             ; Cyclone IV E                                ;
+; Total logic elements               ; 194                                         ;
+;     Total combinational functions  ; 178                                         ;
+;     Dedicated logic registers      ; 122                                         ;
+; Total registers                    ; 122                                         ;
+; Total pins                         ; 37                                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 0                                           ;
+; Embedded Multiplier 9-bit elements ; 0                                           ;
+; Total PLLs                         ; 0                                           ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                              ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                           ; Setting            ; Default Value      ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                           ; EP4CE10E22C8       ;                    ;
+; Top-level entity name                                            ; top                ; template           ;
+; Family name                                                      ; Cyclone IV E       ; Cyclone V          ;
+; Use smart compilation                                            ; Off                ; Off                ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                      ; Off                ; Off                ;
+; Restructure Multiplexers                                         ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
+; Preserve fewer node names                                        ; On                 ; On                 ;
+; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
+; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                         ; Auto               ; Auto               ;
+; Safe State Machine                                               ; Off                ; Off                ;
+; Extract Verilog State Machines                                   ; On                 ; On                 ;
+; Extract VHDL State Machines                                      ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
+; Parallel Synthesis                                               ; On                 ; On                 ;
+; DSP Block Balancing                                              ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                               ; On                 ; On                 ;
+; Power-Up Don't Care                                              ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
+; Remove Duplicate Registers                                       ; On                 ; On                 ;
+; Ignore CARRY Buffers                                             ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
+; Ignore LCELL Buffers                                             ; Off                ; Off                ;
+; Ignore SOFT Buffers                                              ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
+; Optimization Technique                                           ; Balanced           ; Balanced           ;
+; Carry Chain Length                                               ; 70                 ; 70                 ;
+; Auto Carry Chains                                                ; On                 ; On                 ;
+; Auto Open-Drain Pins                                             ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
+; Auto ROM Replacement                                             ; On                 ; On                 ;
+; Auto RAM Replacement                                             ; On                 ; On                 ;
+; Auto DSP Block Replacement                                       ; On                 ; On                 ;
+; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
+; Strict RAM Replacement                                           ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
+; Auto RAM Block Balancing                                         ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                ; Off                ; Off                ;
+; Auto Resource Sharing                                            ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                               ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                               ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                    ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
+; Timing-Driven Synthesis                                          ; On                 ; On                 ;
+; Report Parameter Settings                                        ; On                 ; On                 ;
+; Report Source Assignments                                        ; On                 ; On                 ;
+; Report Connectivity Checks                                       ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
+; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
+; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
+; HDL message level                                                ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
+; Clock MUX Protection                                             ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                      ; Off                ; Off                ;
+; Block Design Naming                                              ; Auto               ; Auto               ;
+; SDC constraint protection                                        ; Off                ; Off                ;
+; Synthesis Effort                                                 ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                             ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                           ; On                 ; On                 ;
++------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
+;     Processors 3-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                    ;
++----------------------------------+-----------------+------------------------+-------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                      ; Library ;
++----------------------------------+-----------------+------------------------+-------------------------------------------------------------------+---------+
+; top.v                            ; yes             ; User Verilog HDL File  ; /home/zen/tmp/a-c4e6e10_exemple/template/top.v                    ;         ;
+; output_files/seg7x8_dp.v         ; yes             ; User Verilog HDL File  ; /home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v ;         ;
++----------------------------------+-----------------+------------------------+-------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                 ;
++---------------------------------------------+---------------+
+; Resource                                    ; Usage         ;
++---------------------------------------------+---------------+
+; Estimated Total logic elements              ; 194           ;
+;                                             ;               ;
+; Total combinational functions               ; 178           ;
+; Logic element usage by number of LUT inputs ;               ;
+;     -- 4 input functions                    ; 53            ;
+;     -- 3 input functions                    ; 10            ;
+;     -- <=2 input functions                  ; 115           ;
+;                                             ;               ;
+; Logic elements by mode                      ;               ;
+;     -- normal mode                          ; 86            ;
+;     -- arithmetic mode                      ; 92            ;
+;                                             ;               ;
+; Total registers                             ; 122           ;
+;     -- Dedicated logic registers            ; 122           ;
+;     -- I/O registers                        ; 0             ;
+;                                             ;               ;
+; I/O pins                                    ; 37            ;
+;                                             ;               ;
+; Embedded Multiplier 9-bit elements          ; 0             ;
+;                                             ;               ;
+; Maximum fan-out node                        ; CLK_50M~input ;
+; Maximum fan-out                             ; 66            ;
+; Total fan-out                               ; 778           ;
+; Average fan-out                             ; 2.08          ;
++---------------------------------------------+---------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                      ;
++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
+; |top                       ; 178 (88)            ; 122 (77)                  ; 0           ; 0            ; 0       ; 0         ; 37   ; 0            ; |top                ; top         ; work         ;
+;    |seg7x8_dp:my|          ; 90 (90)             ; 45 (45)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|seg7x8_dp:my   ; seg7x8_dp   ; work         ;
++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                             ;
++---------------------------------------+----------------------------------------+
+; Register name                         ; Reason for Removal                     ;
++---------------------------------------+----------------------------------------+
+; seg7x8_dp:my|DP                       ; Stuck at GND due to stuck port data_in ;
+; Total Number of Removed Registers = 1 ;                                        ;
++---------------------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 122   ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 4     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; j[0]                                   ; 3       ;
+; seg7x8_dp:my|j[0]                      ; 5       ;
+; Total number of inverted registers = 2 ;         ;
++----------------------------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+; 256:1              ; 4 bits    ; 680 LEs       ; 20 LEs               ; 660 LEs                ; Yes        ; |top|seg7x8_dp:my|n[3]     ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+
+
++------------------------------------------+
+; Port Connectivity Checks: "seg7x8_dp:my" ;
++------+-------+----------+----------------+
+; Port ; Type  ; Severity ; Details        ;
++------+-------+----------+----------------+
+; dp   ; Input ; Info     ; Stuck at GND   ;
++------+-------+----------+----------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; boundary_port         ; 37                          ;
+; cycloneiii_ff         ; 122                         ;
+;     ENA               ; 4                           ;
+;     plain             ; 118                         ;
+; cycloneiii_lcell_comb ; 198                         ;
+;     arith             ; 92                          ;
+;         2 data inputs ; 91                          ;
+;         3 data inputs ; 1                           ;
+;     normal            ; 106                         ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 25                          ;
+;         2 data inputs ; 18                          ;
+;         3 data inputs ; 9                           ;
+;         4 data inputs ; 53                          ;
+;                       ;                             ;
+; Max LUT depth         ; 6.00                        ;
+; Average LUT depth     ; 3.37                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+    Info: Processing started: Sun May 16 23:32:38 2021
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file top.v
+    Info (12023): Found entity 1: top File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file output_files/seg7x8_dp.v
+    Info (12023): Found entity 1: seg7x8_dp File: /home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v Line: 1
+Info (12127): Elaborating entity "top" for the top level hierarchy
+Info (12128): Elaborating entity "seg7x8_dp" for hierarchy "seg7x8_dp:my" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 16
+Info (10264): Verilog HDL Case Statement information at seg7x8_dp.v(54): all case item expressions in this case statement are onehot File: /home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v Line: 54
+Info (10264): Verilog HDL Case Statement information at seg7x8_dp.v(66): all case item expressions in this case statement are onehot File: /home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v Line: 66
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX_S[7]" is stuck at VCC File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 7
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 8 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "SW[1]" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 2
+    Warning (15610): No output dependent on input pin "SW[2]" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 2
+    Warning (15610): No output dependent on input pin "SW[3]" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 2
+    Warning (15610): No output dependent on input pin "SW[4]" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 2
+    Warning (15610): No output dependent on input pin "SW[5]" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 2
+    Warning (15610): No output dependent on input pin "SW[6]" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 2
+    Warning (15610): No output dependent on input pin "SW[7]" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 2
+    Warning (15610): No output dependent on input pin "SW[8]" File: /home/zen/tmp/a-c4e6e10_exemple/template/top.v Line: 2
+Info (21057): Implemented 233 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 9 input pins
+    Info (21059): Implemented 28 output pins
+    Info (21061): Implemented 196 logic cells
+Info (144001): Generated suppressed messages file /home/zen/tmp/a-c4e6e10_exemple/template/output_files/template.map.smsg
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
+    Info: Peak virtual memory: 433 megabytes
+    Info: Processing ended: Sun May 16 23:32:47 2021
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:21
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in /home/zen/tmp/a-c4e6e10_exemple/template/output_files/template.map.smsg.
+
+

counter_test/output_files/template.map.smsg

@@ -0,0 +1 @@
+Info (10281): Verilog HDL Declaration information at seg7x8_dp.v(3): object "dp" differs only in case from object "DP" in the same scope File: /home/zen/tmp/a-c4e6e10_exemple/template/output_files/seg7x8_dp.v Line: 3

counter_test/output_files/template.map.summary

@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Sun May 16 23:32:47 2021
+Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+Revision Name : template
+Top-level Entity Name : top
+Family : Cyclone IV E
+Total logic elements : 194
+    Total combinational functions : 178
+    Dedicated logic registers : 122
+Total registers : 122
+Total pins : 37
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0

counter_test/output_files/template.pin

@@ -0,0 +1,216 @@
+ -- Copyright (C) 2020  Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions 
+ -- and other software and tools, and any partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Intel Program License 
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors.  Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 1:       2.5V
+ --                  Bank 2:       2.5V
+ --                  Bank 3:       2.5V
+ --                  Bank 4:       2.5V
+ --                  Bank 5:       2.5V
+ --                  Bank 6:       2.5V
+ --                  Bank 7:       2.5V
+ --                  Bank 8:       2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+CHIP  "template"  ASSIGNED TO AN: EP4CE10E22C8
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+RESERVED_INPUT_WITH_WEAK_PULLUP : 1         :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 2         :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 3         :        :                   :         : 1         :                
+GND                          : 4         : gnd    :                   :         :           :                
+VCCINT                       : 5         : power  :                   : 1.2V    :           :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 6         : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : 7         :        :                   :         : 1         :                
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 8         : input  : 2.5 V             :         : 1         : N              
+nSTATUS                      : 9         :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 10        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 11        :        :                   :         : 1         :                
+~ALTERA_DCLK~                : 12        : output : 2.5 V             :         : 1         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 13        : input  : 2.5 V             :         : 1         : N              
+nCONFIG                      : 14        :        :                   :         : 1         :                
+TDI                          : 15        : input  :                   :         : 1         :                
+TCK                          : 16        : input  :                   :         : 1         :                
+VCCIO1                       : 17        : power  :                   : 2.5V    : 1         :                
+TMS                          : 18        : input  :                   :         : 1         :                
+GND                          : 19        : gnd    :                   :         :           :                
+TDO                          : 20        : output :                   :         : 1         :                
+nCE                          : 21        :        :                   :         : 1         :                
+GND                          : 22        : gnd    :                   :         :           :                
+CLK_50M                      : 23        : input  : 2.5 V             :         : 1         : Y              
+GND+                         : 24        :        :                   :         : 2         :                
+GND+                         : 25        :        :                   :         : 2         :                
+VCCIO2                       : 26        : power  :                   : 2.5V    : 2         :                
+GND                          : 27        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 28        :        :                   :         : 2         :                
+VCCINT                       : 29        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 30        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 31        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 32        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 33        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 34        :        :                   :         : 2         :                
+VCCA1                        : 35        : power  :                   : 2.5V    :           :                
+GNDA1                        : 36        : gnd    :                   :         :           :                
+VCCD_PLL1                    : 37        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 38        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 39        :        :                   :         : 3         :                
+VCCIO3                       : 40        : power  :                   : 2.5V    : 3         :                
+GND                          : 41        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 42        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 43        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 44        :        :                   :         : 3         :                
+VCCINT                       : 45        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 46        :        :                   :         : 3         :                
+VCCIO3                       : 47        : power  :                   : 2.5V    : 3         :                
+GND                          : 48        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 49        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 50        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 51        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 52        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 53        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 54        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 55        :        :                   :         : 4         :                
+VCCIO4                       : 56        : power  :                   : 2.5V    : 4         :                
+GND                          : 57        : gnd    :                   :         :           :                
+SW[1]                        : 58        : input  : 2.5 V             :         : 4         : Y              
+SW[2]                        : 59        : input  : 2.5 V             :         : 4         : Y              
+SW[3]                        : 60        : input  : 2.5 V             :         : 4         : Y              
+VCCINT                       : 61        : power  :                   : 1.2V    :           :                
+VCCIO4                       : 62        : power  :                   : 2.5V    : 4         :                
+GND                          : 63        : gnd    :                   :         :           :                
+SW[4]                        : 64        : input  : 2.5 V             :         : 4         : Y              
+SW[5]                        : 65        : input  : 2.5 V             :         : 4         : Y              
+SW[6]                        : 66        : input  : 2.5 V             :         : 4         : Y              
+SW[7]                        : 67        : input  : 2.5 V             :         : 4         : Y              
+SW[8]                        : 68        : input  : 2.5 V             :         : 4         : Y              
+D[14]                        : 69        : output : 2.5 V             :         : 4         : Y              
+D[13]                        : 70        : output : 2.5 V             :         : 4         : Y              
+D[12]                        : 71        : output : 2.5 V             :         : 4         : Y              
+D[3]                         : 72        : output : 2.5 V             :         : 4         : Y              
+D[4]                         : 73        : output : 2.5 V             :         : 5         : Y              
+D[5]                         : 74        : output : 2.5 V             :         : 5         : Y              
+D[11]                        : 75        : output : 2.5 V             :         : 5         : Y              
+D[10]                        : 76        : output : 2.5 V             :         : 5         : Y              
+D[9]                         : 77        : output : 2.5 V             :         : 5         : Y              
+VCCINT                       : 78        : power  :                   : 1.2V    :           :                
+GND                          : 79        : gnd    :                   :         :           :                
+D[6]                         : 80        : output : 2.5 V             :         : 5         : Y              
+VCCIO5                       : 81        : power  :                   : 2.5V    : 5         :                
+GND                          : 82        : gnd    :                   :         :           :                
+D[7]                         : 83        : output : 2.5 V             :         : 5         : Y              
+D[8]                         : 84        : output : 2.5 V             :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : 85        :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 86        :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 87        :        :                   :         : 5         :                
+GND+                         : 88        :        :                   :         : 5         :                
+GND+                         : 89        :        :                   :         : 5         :                
+GND+                         : 90        :        :                   :         : 6         :                
+GND+                         : 91        :        :                   :         : 6         :                
+CONF_DONE                    : 92        :        :                   :         : 6         :                
+VCCIO6                       : 93        : power  :                   : 2.5V    : 6         :                
+MSEL0                        : 94        :        :                   :         : 6         :                
+GND                          : 95        : gnd    :                   :         :           :                
+MSEL1                        : 96        :        :                   :         : 6         :                
+MSEL2                        : 97        :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 98        :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 99        :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 100       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 101       : output : 2.5 V             :         : 6         : N              
+VCCINT                       : 102       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 103       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 104       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 105       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 106       :        :                   :         : 6         :                
+VCCA2                        : 107       : power  :                   : 2.5V    :           :                
+GNDA2                        : 108       : gnd    :                   :         :           :                
+VCCD_PLL2                    : 109       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 110       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 111       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 112       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 113       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 114       :        :                   :         : 7         :                
+HEX_S[7]                     : 115       : output : 2.5 V             :         : 7         : Y              
+VCCINT                       : 116       : power  :                   : 1.2V    :           :                
+VCCIO7                       : 117       : power  :                   : 2.5V    : 7         :                
+GND                          : 118       : gnd    :                   :         :           :                
+HEX_S[6]                     : 119       : output : 2.5 V             :         : 7         : Y              
+HEX_S[5]                     : 120       : output : 2.5 V             :         : 7         : Y              
+HEX_S[4]                     : 121       : output : 2.5 V             :         : 7         : Y              
+VCCIO7                       : 122       : power  :                   : 2.5V    : 7         :                
+GND                          : 123       : gnd    :                   :         :           :                
+HEX_S[3]                     : 124       : output : 2.5 V             :         : 7         : Y              
+HEX_S[2]                     : 125       : output : 2.5 V             :         : 7         : Y              
+HEX_S[1]                     : 126       : output : 2.5 V             :         : 7         : Y              
+HEX_S[0]                     : 127       : output : 2.5 V             :         : 7         : Y              
+HEX[0]                       : 128       : output : 2.5 V             :         : 8         : Y              
+HEX[1]                       : 129       : output : 2.5 V             :         : 8         : Y              
+VCCIO8                       : 130       : power  :                   : 2.5V    : 8         :                
+GND                          : 131       : gnd    :                   :         :           :                
+HEX[2]                       : 132       : output : 2.5 V             :         : 8         : Y              
+HEX[3]                       : 133       : output : 2.5 V             :         : 8         : Y              
+VCCINT                       : 134       : power  :                   : 1.2V    :           :                
+HEX[4]                       : 135       : output : 2.5 V             :         : 8         : Y              
+HEX[5]                       : 136       : output : 2.5 V             :         : 8         : Y              
+HEX[6]                       : 137       : output : 2.5 V             :         : 8         : Y              
+HEX[7]                       : 138       : output : 2.5 V             :         : 8         : Y              
+VCCIO8                       : 139       : power  :                   : 2.5V    : 8         :                
+GND                          : 140       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 141       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 142       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 143       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : 144       :        :                   :         : 8         :                
+GND                          : EPAD      :        :                   :         :           :                

counter_test/output_files/template.sld

@@ -0,0 +1 @@
+<sld_project_info/>

counter_test/output_files/template.sta.summary

@@ -0,0 +1,113 @@
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'CLK_50M'
+Slack : -3.547
+TNS   : -155.487
+
+Type  : Slow 1200mV 85C Model Setup 'seg7x8_dp:my|y'
+Slack : -3.088
+TNS   : -17.556
+
+Type  : Slow 1200mV 85C Model Setup 'y'
+Slack : -2.899
+TNS   : -67.661
+
+Type  : Slow 1200mV 85C Model Hold 'y'
+Slack : 0.516
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'CLK_50M'
+Slack : 0.634
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'seg7x8_dp:my|y'
+Slack : 0.738
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLK_50M'
+Slack : -3.000
+TNS   : -101.142
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'y'
+Slack : -1.487
+TNS   : -65.428
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'seg7x8_dp:my|y'
+Slack : -1.487
+TNS   : -17.844
+
+Type  : Slow 1200mV 0C Model Setup 'CLK_50M'
+Slack : -3.201
+TNS   : -133.733
+
+Type  : Slow 1200mV 0C Model Setup 'seg7x8_dp:my|y'
+Slack : -2.838
+TNS   : -15.657
+
+Type  : Slow 1200mV 0C Model Setup 'y'
+Slack : -2.490
+TNS   : -57.440
+
+Type  : Slow 1200mV 0C Model Hold 'y'
+Slack : 0.477
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLK_50M'
+Slack : 0.566
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'seg7x8_dp:my|y'
+Slack : 0.676
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLK_50M'
+Slack : -3.000
+TNS   : -101.142
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'y'
+Slack : -1.487
+TNS   : -65.428
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'seg7x8_dp:my|y'
+Slack : -1.487
+TNS   : -17.844
+
+Type  : Fast 1200mV 0C Model Setup 'CLK_50M'
+Slack : -0.883
+TNS   : -30.950
+
+Type  : Fast 1200mV 0C Model Setup 'seg7x8_dp:my|y'
+Slack : -0.793
+TNS   : -3.418
+
+Type  : Fast 1200mV 0C Model Setup 'y'
+Slack : -0.741
+TNS   : -10.730
+
+Type  : Fast 1200mV 0C Model Hold 'y'
+Slack : 0.210
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'CLK_50M'
+Slack : 0.265
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'seg7x8_dp:my|y'
+Slack : 0.287
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLK_50M'
+Slack : -3.000
+TNS   : -73.376
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'y'
+Slack : -1.000
+TNS   : -44.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'seg7x8_dp:my|y'
+Slack : -1.000
+TNS   : -12.000
+
+------------------------------------------------------------

counter_test/template.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 20:32:51  October 18, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "20:32:51  October 18, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "template"

counter_test/template.qsf

@@ -0,0 +1,120 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 20:32:51  October 18, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		template_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE10E22C8
+set_global_assignment -name TOP_LEVEL_ENTITY top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:51  OCTOBER 18, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_location_assignment PIN_128 -to HEX[0]
+set_location_assignment PIN_129 -to HEX[1]
+set_location_assignment PIN_132 -to HEX[2]
+set_location_assignment PIN_133 -to HEX[3]
+set_location_assignment PIN_135 -to HEX[4]
+set_location_assignment PIN_136 -to HEX[5]
+set_location_assignment PIN_137 -to HEX[6]
+set_location_assignment PIN_138 -to HEX[7]
+set_location_assignment PIN_72 -to D[3]
+set_location_assignment PIN_73 -to D[4]
+set_location_assignment PIN_74 -to D[5]
+set_location_assignment PIN_80 -to D[6]
+set_location_assignment PIN_83 -to D[7]
+set_location_assignment PIN_84 -to D[8]
+set_location_assignment PIN_77 -to D[9]
+set_location_assignment PIN_76 -to D[10]
+set_location_assignment PIN_75 -to D[11]
+set_location_assignment PIN_71 -to D[12]
+set_location_assignment PIN_70 -to D[13]
+set_location_assignment PIN_69 -to D[14]
+set_location_assignment PIN_58 -to SW[1]
+set_location_assignment PIN_60 -to SW[3]
+set_location_assignment PIN_64 -to SW[4]
+set_location_assignment PIN_65 -to SW[5]
+set_location_assignment PIN_66 -to SW[6]
+set_location_assignment PIN_67 -to SW[7]
+set_location_assignment PIN_59 -to SW[2]
+set_location_assignment PIN_68 -to SW[8]
+set_location_assignment PIN_90 -to K[2]
+set_location_assignment PIN_91 -to K[3]
+set_location_assignment PIN_87 -to K[4]
+set_location_assignment PIN_86 -to K[5]
+set_location_assignment PIN_141 -to BELL
+set_location_assignment PIN_2 -to VGA_R
+set_location_assignment PIN_1 -to VGA_G
+set_location_assignment PIN_144 -to VGA_B
+set_location_assignment PIN_143 -to VGA_VS
+set_location_assignment PIN_142 -to VGA_HS
+set_location_assignment PIN_3 -to MEM_SDA
+set_location_assignment PIN_7 -to MEM_SCK
+set_location_assignment PIN_10 -to PS_2_DATA
+set_location_assignment PIN_11 -to PS_2_SCK
+set_location_assignment PIN_23 -to CLK_50M
+set_location_assignment PIN_24 -to CLK_USER
+set_location_assignment PIN_114 -to UART_TX
+set_location_assignment PIN_113 -to UART_RX
+set_location_assignment PIN_101 -to LCD_D[0]
+set_location_assignment PIN_103 -to LCD_D[1]
+set_location_assignment PIN_104 -to LCD_D[2]
+set_location_assignment PIN_105 -to LCD_D[3]
+set_location_assignment PIN_106 -to LCD_D[4]
+set_location_assignment PIN_110 -to LCD_D[5]
+set_location_assignment PIN_111 -to LCD_D[6]
+set_location_assignment PIN_112 -to LCD_D[7]
+set_location_assignment PIN_85 -to LCD_RS
+set_location_assignment PIN_99 -to LCD_WR
+set_location_assignment PIN_100 -to LCD_EN
+set_global_assignment -name VERILOG_FILE top.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_127 -to HEX_S[0]
+set_location_assignment PIN_126 -to HEX_S[1]
+set_location_assignment PIN_125 -to HEX_S[2]
+set_location_assignment PIN_124 -to HEX_S[3]
+set_location_assignment PIN_121 -to HEX_S[4]
+set_location_assignment PIN_120 -to HEX_S[5]
+set_location_assignment PIN_119 -to HEX_S[6]
+set_location_assignment PIN_115 -to HEX_S[7]
+set_global_assignment -name VERILOG_FILE output_files/seg7x8_dp.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top