add template

master
zen 3 years ago
parent f83a516697
commit 861507d867
  1. 25
      AHDL_test/7seg_driver.inc
  2. 23
      AHDL_test/7seg_driver.tdf
  3. 25
      AHDL_test/7seg_driver.tdf.bak
  4. 58
      AHDL_test/LED_7seg_driver.bsf
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      AHDL_test/db/.cmp.kpt
  6. 58
      AHDL_test/db/prev_cmp_template.qmsg
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      AHDL_test/db/template.cmp.bpm
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      AHDL_test/db/template.cmp.cdb
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      AHDL_test/db/template.cmp.hdb
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      AHDL_test/db/template.cmp.logdb
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      AHDL_test/db/template.cmp.rdb
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      AHDL_test/db/template.cmp_merge.kpt
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      AHDL_test/db/template.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
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      AHDL_test/db/template.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
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      AHDL_test/db/template.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
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      AHDL_test/db/template.fit.qmsg
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      AHDL_test/db/template.hier_info
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      AHDL_test/db/template.lpc.html
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      AHDL_test/db/template.lpc.txt
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      AHDL_test/db/template.map.bpm
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      AHDL_test/db/template.map.cdb
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      AHDL_test/db/template.map.kpt
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      AHDL_test/db/template.pre_map.hdb
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      AHDL_test/db/template.root_partition.map.reg_db.cdb
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      AHDL_test/db/template.routing.rdb
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      AHDL_test/db/template.sld_design_entry.sci
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      AHDL_test/db/template.vpr.ammdb
  68. 57
      AHDL_test/db/template_partition_pins.json
  69. 11
      AHDL_test/incremental_db/README
  70. 3
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      AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.ammdb
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      AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.cdb
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      AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.dfp
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      AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.hdb
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      AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.dpi
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      AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.cdb
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      AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.kpt
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      AHDL_test/incremental_db/compiled_partitions/template.rrp.hdb
  86. 92
      AHDL_test/output_files/template.asm.rpt
  87. 1
      AHDL_test/output_files/template.done
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      AHDL_test/output_files/template.fit.rpt
  89. 8
      AHDL_test/output_files/template.fit.smsg
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      AHDL_test/output_files/template.fit.summary
  91. 124
      AHDL_test/output_files/template.flow.rpt
  92. 8
      AHDL_test/output_files/template.jdi
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      AHDL_test/output_files/template.map.rpt
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      AHDL_test/output_files/template.map.summary
  95. 216
      AHDL_test/output_files/template.pin
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      AHDL_test/output_files/template.sta.rpt
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      AHDL_test/output_files/template.sta.summary
  100. 163
      AHDL_test/template.bdf
  101. Some files were not shown because too many files have changed in this diff Show More

@ -0,0 +1,25 @@
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
-- Generated by Quartus Prime Version 20.1 (Build Build 720 11/11/2020)
-- Created on Sat Apr 24 03:39:58 2021
FUNCTION 7seg_driver (D[3..0])
RETURNS (SEG[6..0]);

@ -0,0 +1,23 @@
subdesign 7seg_driver (D[3..0]: input = VCC; SEG[6..0]: output;)
begin
case d[] is
when 0 => SEG[6..0] = b"0000001";
when 1 => SEG[6..0] = b"1001111";
when 2 => SEG[6..0] = b"0010010";
when 3 => SEG[6..0] = b"0000110";
when 4 => SEG[6..0] = b"1001100";
when 5 => SEG[6..0] = b"0100100";
when 6 => SEG[6..0] = b"0100000";
when 7 => SEG[6..0] = b"0001111";
when 8 => SEG[6..0] = b"0000000";
when 9 => SEG[6..0] = b"0000100";
when 10 => SEG[6..0] = b"0001000";
when 11 => SEG[6..0] = b"1100000";
when 12 => SEG[6..0] = b"0110001";
when 13 => SEG[6..0] = b"1000010";
when 14 => SEG[6..0] = b"0110000";
when 15 => SEG[6..0] = b"0111000";
when others => SEG[6..0] = VCC;
end case;
end;

@ -0,0 +1,25 @@
subdesign 7seg_driver (DP, D[0..3]: input = VCC; SEG[0..7]: output;)
begin
SEG[7] = DP;
case d[] is
when 0 => SEG[0..6] = b"0000001";
when 1 => SEG[0..6] = b"1001111";
when 2 => SEG[0..6] = b"0010010";
when 3 => SEG[0..6] = b"0000110";
when 4 => SEG[0..6] = b"1001100";
when 5 => SEG[0..6] = b"0100100";
when 6 => SEG[0..6] = b"0100000";
when 7 => SEG[0..6] = b"0001111";
when 8 => SEG[0..6] = b"0000000";
when 9 => SEG[0..6] = b"0000100";
when 10 => SEG[0..6] = b"0001000";
when 11 => SEG[0..6] = b"1100000";
when 12 => SEG[0..6] = b"0110001";
when 13 => SEG[0..6] = b"1000010";
when 14 => SEG[0..6] = b"0110000";
when 15 => SEG[0..6] = b"0111000";
when others => SEG[0..6] = VCC;
end case;
end;

@ -0,0 +1,58 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 208 96)
(text "LED_7seg_driver" (rect 5 0 79 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "D[0..7][0..4]" (rect 0 0 48 12)(font "Arial" ))
(text "D[0..7][0..4]" (rect 21 27 69 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 43 31 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 192 32)
(output)
(text "dig[0..7]" (rect 0 0 30 12)(font "Arial" ))
(text "dig[0..7]" (rect 141 27 171 39)(font "Arial" ))
(line (pt 192 32)(pt 176 32)(line_width 3))
)
(port
(pt 192 48)
(output)
(text "SEG[6..0]" (rect 0 0 40 12)(font "Arial" ))
(text "SEG[6..0]" (rect 131 43 171 55)(font "Arial" ))
(line (pt 192 48)(pt 176 48)(line_width 3))
)
(drawing
(rectangle (rect 16 16 176 64)(line_width 1))
)
)

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@ -0,0 +1,58 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224882172 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224882172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:41:22 2021 " "Processing started: Sat Apr 24 03:41:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224882172 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224882172 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224882173 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619224882360 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619224882360 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf " "Can't analyze file -- file ../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1619224889452 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.bdf 1 1 " "Found 1 design units, including 1 entities, in source file template.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 template " "Found entity 1: template" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224889453 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889453 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 7 " "Group MSB D7 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224889456 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 3 " "Group MSB D3 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224889456 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "dig 7 " "Group MSB dig7 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 5 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224889456 ""}
{ "Warning" "WTDFX_RANGE_CONFLICT" "D 7 0 D 0 7 " "Group is used as \"D\[7..0\]\" and defined using a different range order (\"D\[0..7\]\")" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } } } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224889457 ""}
{ "Warning" "WTDFX_RANGE_CONFLICT" "D 3 0 D 0 3 " "Group is used as \"D\[3..0\]\" and defined using a different range order (\"D\[0..3\]\")" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } } } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224889457 ""}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "decoder_out " "Variable or input pin \"decoder_out\" is defined but never used." { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 10 16 0 } } } 0 287013 "Variable or input pin \"%1!s!\" is defined but never used." 0 0 "Analysis & Synthesis" 0 -1 1619224889457 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.tdf 1 1 " "Found 1 design units, including 1 entities, in source file template.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 LED_7seg_driver " "Found entity 1: LED_7seg_driver" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224889457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889457 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "7seg_driver.tdf 1 1 " "Found 1 design units, including 1 entities, in source file 7seg_driver.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7seg_driver " "Found entity 1: 7seg_driver" { } { { "7seg_driver.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/7seg_driver.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224889458 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889458 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 8 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number0 " "Symbolic name \"number0\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 8 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 8 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 9 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number1 " "Symbolic name \"number1\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 9 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 9 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 10 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number2 " "Symbolic name \"number2\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 10 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 10 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 11 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number3 " "Symbolic name \"number3\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 11 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 11 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 12 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number4 " "Symbolic name \"number4\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 12 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 12 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 13 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number5 " "Symbolic name \"number5\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 13 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 13 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 14 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number6 " "Symbolic name \"number6\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 14 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 14 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 15 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number7 " "Symbolic name \"number7\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 15 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 15 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 17 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 17 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 18 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 18 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 19 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 19 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 20 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 20 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 21 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 21 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 22 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 22 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 23 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 23 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""}
{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 24 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889460 ""}
{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 24 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889460 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.tdf 0 0 " "Found 0 design units, including 0 entities, in source file test.tdf" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889460 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 24 s 24 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 24 errors, 24 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "354 " "Peak virtual memory: 354 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224889497 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Apr 24 03:41:29 2021 " "Processing ended: Sat Apr 24 03:41:29 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224889497 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224889497 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224889497 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889497 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 26 s 24 s " "Quartus Prime Full Compilation was unsuccessful. 26 errors, 24 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889604 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224941420 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224941421 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:21 2021 " "Processing started: Sat Apr 24 03:42:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224941421 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619224941421 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off template -c template " "Command: quartus_asm --read_settings_files=off --write_settings_files=off template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619224941421 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619224941606 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619224941873 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619224941888 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Peak virtual memory: 351 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:21 2021 " "Processing ended: Sat Apr 24 03:42:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619224941963 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="template">
</PROJECT>
</LOG_ROOT>

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v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,0;17;17;0;0;17;17;0;0;0;0;0;0;15;0;0;0;2;15;0;2;0;0;15;0;17;17;17;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,17;0;0;17;17;0;0;17;17;17;17;17;17;2;17;17;17;15;2;17;15;17;17;2;17;0;0;0;17;17,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,HEX[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SEG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SEG[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SEG[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SEG[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SEG[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SEG[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SEG[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,K[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,K[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,

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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Fri Apr 23 19:24:53 2021

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|template
HEX[7] <= LED_7seg_driver:inst.dig[7]
HEX[6] <= LED_7seg_driver:inst.dig[6]
HEX[5] <= LED_7seg_driver:inst.dig[5]
HEX[4] <= LED_7seg_driver:inst.dig[4]
HEX[3] <= LED_7seg_driver:inst.dig[3]
HEX[2] <= LED_7seg_driver:inst.dig[2]
HEX[1] <= LED_7seg_driver:inst.dig[1]
HEX[0] <= LED_7seg_driver:inst.dig[0]
K[2] => LED_7seg_driver:inst.clk
K[3] => test:inst4.test
SEG[6] <= LED_7seg_driver:inst.SEG[0]
SEG[5] <= LED_7seg_driver:inst.SEG[1]
SEG[4] <= LED_7seg_driver:inst.SEG[2]
SEG[3] <= LED_7seg_driver:inst.SEG[3]
SEG[2] <= LED_7seg_driver:inst.SEG[4]
SEG[1] <= LED_7seg_driver:inst.SEG[5]
SEG[0] <= LED_7seg_driver:inst.SEG[6]
|template|LED_7seg_driver:inst
D[7][3] => in_buf[7][3].DATAIN
D[7][2] => in_buf[7][2].DATAIN
D[7][1] => in_buf[7][1].DATAIN
D[7][0] => in_buf[7][0].DATAIN
D[6][3] => in_buf[6][3].DATAIN
D[6][2] => in_buf[6][2].DATAIN
D[6][1] => in_buf[6][1].DATAIN
D[6][0] => in_buf[6][0].DATAIN
D[5][3] => in_buf[5][3].DATAIN
D[5][2] => in_buf[5][2].DATAIN
D[5][1] => in_buf[5][1].DATAIN
D[5][0] => in_buf[5][0].DATAIN
D[4][3] => in_buf[4][3].DATAIN
D[4][2] => in_buf[4][2].DATAIN
D[4][1] => in_buf[4][1].DATAIN
D[4][0] => in_buf[4][0].DATAIN
D[3][3] => in_buf[3][3].DATAIN
D[3][2] => in_buf[3][2].DATAIN
D[3][1] => in_buf[3][1].DATAIN
D[3][0] => in_buf[3][0].DATAIN
D[2][3] => in_buf[2][3].DATAIN
D[2][2] => in_buf[2][2].DATAIN
D[2][1] => in_buf[2][1].DATAIN
D[2][0] => in_buf[2][0].DATAIN
D[1][3] => in_buf[1][3].DATAIN
D[1][2] => in_buf[1][2].DATAIN
D[1][1] => in_buf[1][1].DATAIN
D[1][0] => in_buf[1][0].DATAIN
D[0][3] => in_buf[0][3].DATAIN
D[0][2] => in_buf[0][2].DATAIN
D[0][1] => in_buf[0][1].DATAIN
D[0][0] => in_buf[0][0].DATAIN
clk => in_buf[7][3].CLK
clk => in_buf[7][2].CLK
clk => in_buf[7][1].CLK
clk => in_buf[7][0].CLK
clk => in_buf[6][3].CLK
clk => in_buf[6][2].CLK
clk => in_buf[6][1].CLK
clk => in_buf[6][0].CLK
clk => in_buf[5][3].CLK
clk => in_buf[5][2].CLK
clk => in_buf[5][1].CLK
clk => in_buf[5][0].CLK
clk => in_buf[4][3].CLK
clk => in_buf[4][2].CLK
clk => in_buf[4][1].CLK
clk => in_buf[4][0].CLK
clk => in_buf[3][3].CLK
clk => in_buf[3][2].CLK
clk => in_buf[3][1].CLK
clk => in_buf[3][0].CLK
clk => in_buf[2][3].CLK
clk => in_buf[2][2].CLK
clk => in_buf[2][1].CLK
clk => in_buf[2][0].CLK
clk => in_buf[1][3].CLK
clk => in_buf[1][2].CLK
clk => in_buf[1][1].CLK
clk => in_buf[1][0].CLK
clk => in_buf[0][3].CLK
clk => in_buf[0][2].CLK
clk => in_buf[0][1].CLK
clk => in_buf[0][0].CLK
clk => switcher[3].CLK
clk => switcher[2].CLK
clk => switcher[1].CLK
clk => switcher[0].CLK
dig[7] <= dig[7].DB_MAX_OUTPUT_PORT_TYPE
dig[6] <= dig[6].DB_MAX_OUTPUT_PORT_TYPE
dig[5] <= dig[5].DB_MAX_OUTPUT_PORT_TYPE
dig[4] <= dig[4].DB_MAX_OUTPUT_PORT_TYPE
dig[3] <= dig[3].DB_MAX_OUTPUT_PORT_TYPE
dig[2] <= dig[2].DB_MAX_OUTPUT_PORT_TYPE
dig[1] <= dig[1].DB_MAX_OUTPUT_PORT_TYPE
dig[0] <= dig[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|LED_7seg_driver:inst|7seg_driver:$00000
D[0] => _.IN0
D[0] => SEG[6]~2.IN3
D[0] => _.IN0
D[0] => SEG[2]~4.IN3
D[0] => _.IN0
D[0] => SEG[5]~6.IN3
D[0] => _.IN0
D[0] => SEG[3]~8.IN3
D[0] => _.IN0
D[0] => SEG[2]~9.IN3
D[0] => _.IN0
D[0] => SEG[6]~11.IN3
D[0] => _.IN0
D[0] => SEG[6]~13.IN3
D[0] => _.IN0
D[0] => SEG[5]~15.IN3
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[4]~3.IN2
D[1] => SEG[2]~4.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~7.IN2
D[1] => SEG[3]~8.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[3]~10.IN2
D[1] => SEG[6]~11.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~14.IN2
D[1] => SEG[5]~15.IN2
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[6]~5.IN1
D[2] => SEG[5]~6.IN1
D[2] => SEG[5]~7.IN1
D[2] => SEG[3]~8.IN1
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[5]~12.IN1
D[2] => SEG[6]~13.IN1
D[2] => SEG[5]~14.IN1
D[2] => SEG[5]~15.IN1
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => SEG[2]~9.IN0
D[3] => SEG[3]~10.IN0
D[3] => SEG[6]~11.IN0
D[3] => SEG[5]~12.IN0
D[3] => SEG[6]~13.IN0
D[3] => SEG[5]~14.IN0
D[3] => SEG[5]~15.IN0
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|LED_7seg_driver:inst|7seg_driver:$00002
D[0] => _.IN0
D[0] => SEG[6]~2.IN3
D[0] => _.IN0
D[0] => SEG[2]~4.IN3
D[0] => _.IN0
D[0] => SEG[5]~6.IN3
D[0] => _.IN0
D[0] => SEG[3]~8.IN3
D[0] => _.IN0
D[0] => SEG[2]~9.IN3
D[0] => _.IN0
D[0] => SEG[6]~11.IN3
D[0] => _.IN0
D[0] => SEG[6]~13.IN3
D[0] => _.IN0
D[0] => SEG[5]~15.IN3
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[4]~3.IN2
D[1] => SEG[2]~4.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~7.IN2
D[1] => SEG[3]~8.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[3]~10.IN2
D[1] => SEG[6]~11.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~14.IN2
D[1] => SEG[5]~15.IN2
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[6]~5.IN1
D[2] => SEG[5]~6.IN1
D[2] => SEG[5]~7.IN1
D[2] => SEG[3]~8.IN1
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[5]~12.IN1
D[2] => SEG[6]~13.IN1
D[2] => SEG[5]~14.IN1
D[2] => SEG[5]~15.IN1
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => SEG[2]~9.IN0
D[3] => SEG[3]~10.IN0
D[3] => SEG[6]~11.IN0
D[3] => SEG[5]~12.IN0
D[3] => SEG[6]~13.IN0
D[3] => SEG[5]~14.IN0
D[3] => SEG[5]~15.IN0
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|LED_7seg_driver:inst|7seg_driver:$00004
D[0] => _.IN0
D[0] => SEG[6]~2.IN3
D[0] => _.IN0
D[0] => SEG[2]~4.IN3
D[0] => _.IN0
D[0] => SEG[5]~6.IN3
D[0] => _.IN0
D[0] => SEG[3]~8.IN3
D[0] => _.IN0
D[0] => SEG[2]~9.IN3
D[0] => _.IN0
D[0] => SEG[6]~11.IN3
D[0] => _.IN0
D[0] => SEG[6]~13.IN3
D[0] => _.IN0
D[0] => SEG[5]~15.IN3
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[4]~3.IN2
D[1] => SEG[2]~4.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~7.IN2
D[1] => SEG[3]~8.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[3]~10.IN2
D[1] => SEG[6]~11.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~14.IN2
D[1] => SEG[5]~15.IN2
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[6]~5.IN1
D[2] => SEG[5]~6.IN1
D[2] => SEG[5]~7.IN1
D[2] => SEG[3]~8.IN1
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[5]~12.IN1
D[2] => SEG[6]~13.IN1
D[2] => SEG[5]~14.IN1
D[2] => SEG[5]~15.IN1
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => SEG[2]~9.IN0
D[3] => SEG[3]~10.IN0
D[3] => SEG[6]~11.IN0
D[3] => SEG[5]~12.IN0
D[3] => SEG[6]~13.IN0
D[3] => SEG[5]~14.IN0
D[3] => SEG[5]~15.IN0
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|LED_7seg_driver:inst|7seg_driver:$00006
D[0] => _.IN0
D[0] => SEG[6]~2.IN3
D[0] => _.IN0
D[0] => SEG[2]~4.IN3
D[0] => _.IN0
D[0] => SEG[5]~6.IN3
D[0] => _.IN0
D[0] => SEG[3]~8.IN3
D[0] => _.IN0
D[0] => SEG[2]~9.IN3
D[0] => _.IN0
D[0] => SEG[6]~11.IN3
D[0] => _.IN0
D[0] => SEG[6]~13.IN3
D[0] => _.IN0
D[0] => SEG[5]~15.IN3
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[4]~3.IN2
D[1] => SEG[2]~4.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~7.IN2
D[1] => SEG[3]~8.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[3]~10.IN2
D[1] => SEG[6]~11.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~14.IN2
D[1] => SEG[5]~15.IN2
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[6]~5.IN1
D[2] => SEG[5]~6.IN1
D[2] => SEG[5]~7.IN1
D[2] => SEG[3]~8.IN1
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[5]~12.IN1
D[2] => SEG[6]~13.IN1
D[2] => SEG[5]~14.IN1
D[2] => SEG[5]~15.IN1
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => SEG[2]~9.IN0
D[3] => SEG[3]~10.IN0
D[3] => SEG[6]~11.IN0
D[3] => SEG[5]~12.IN0
D[3] => SEG[6]~13.IN0
D[3] => SEG[5]~14.IN0
D[3] => SEG[5]~15.IN0
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|LED_7seg_driver:inst|7seg_driver:$00008
D[0] => _.IN0
D[0] => SEG[6]~2.IN3
D[0] => _.IN0
D[0] => SEG[2]~4.IN3
D[0] => _.IN0
D[0] => SEG[5]~6.IN3
D[0] => _.IN0
D[0] => SEG[3]~8.IN3
D[0] => _.IN0
D[0] => SEG[2]~9.IN3
D[0] => _.IN0
D[0] => SEG[6]~11.IN3
D[0] => _.IN0
D[0] => SEG[6]~13.IN3
D[0] => _.IN0
D[0] => SEG[5]~15.IN3
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[4]~3.IN2
D[1] => SEG[2]~4.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~7.IN2
D[1] => SEG[3]~8.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[3]~10.IN2
D[1] => SEG[6]~11.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~14.IN2
D[1] => SEG[5]~15.IN2
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[6]~5.IN1
D[2] => SEG[5]~6.IN1
D[2] => SEG[5]~7.IN1
D[2] => SEG[3]~8.IN1
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[5]~12.IN1
D[2] => SEG[6]~13.IN1
D[2] => SEG[5]~14.IN1
D[2] => SEG[5]~15.IN1
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => SEG[2]~9.IN0
D[3] => SEG[3]~10.IN0
D[3] => SEG[6]~11.IN0
D[3] => SEG[5]~12.IN0
D[3] => SEG[6]~13.IN0
D[3] => SEG[5]~14.IN0
D[3] => SEG[5]~15.IN0
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|LED_7seg_driver:inst|7seg_driver:$00010
D[0] => _.IN0
D[0] => SEG[6]~2.IN3
D[0] => _.IN0
D[0] => SEG[2]~4.IN3
D[0] => _.IN0
D[0] => SEG[5]~6.IN3
D[0] => _.IN0
D[0] => SEG[3]~8.IN3
D[0] => _.IN0
D[0] => SEG[2]~9.IN3
D[0] => _.IN0
D[0] => SEG[6]~11.IN3
D[0] => _.IN0
D[0] => SEG[6]~13.IN3
D[0] => _.IN0
D[0] => SEG[5]~15.IN3
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[4]~3.IN2
D[1] => SEG[2]~4.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~7.IN2
D[1] => SEG[3]~8.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[3]~10.IN2
D[1] => SEG[6]~11.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~14.IN2
D[1] => SEG[5]~15.IN2
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[6]~5.IN1
D[2] => SEG[5]~6.IN1
D[2] => SEG[5]~7.IN1
D[2] => SEG[3]~8.IN1
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[5]~12.IN1
D[2] => SEG[6]~13.IN1
D[2] => SEG[5]~14.IN1
D[2] => SEG[5]~15.IN1
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => SEG[2]~9.IN0
D[3] => SEG[3]~10.IN0
D[3] => SEG[6]~11.IN0
D[3] => SEG[5]~12.IN0
D[3] => SEG[6]~13.IN0
D[3] => SEG[5]~14.IN0
D[3] => SEG[5]~15.IN0
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|LED_7seg_driver:inst|7seg_driver:$00012
D[0] => _.IN0
D[0] => SEG[6]~2.IN3
D[0] => _.IN0
D[0] => SEG[2]~4.IN3
D[0] => _.IN0
D[0] => SEG[5]~6.IN3
D[0] => _.IN0
D[0] => SEG[3]~8.IN3
D[0] => _.IN0
D[0] => SEG[2]~9.IN3
D[0] => _.IN0
D[0] => SEG[6]~11.IN3
D[0] => _.IN0
D[0] => SEG[6]~13.IN3
D[0] => _.IN0
D[0] => SEG[5]~15.IN3
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[4]~3.IN2
D[1] => SEG[2]~4.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~7.IN2
D[1] => SEG[3]~8.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[3]~10.IN2
D[1] => SEG[6]~11.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~14.IN2
D[1] => SEG[5]~15.IN2
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[6]~5.IN1
D[2] => SEG[5]~6.IN1
D[2] => SEG[5]~7.IN1
D[2] => SEG[3]~8.IN1
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[5]~12.IN1
D[2] => SEG[6]~13.IN1
D[2] => SEG[5]~14.IN1
D[2] => SEG[5]~15.IN1
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => SEG[2]~9.IN0
D[3] => SEG[3]~10.IN0
D[3] => SEG[6]~11.IN0
D[3] => SEG[5]~12.IN0
D[3] => SEG[6]~13.IN0
D[3] => SEG[5]~14.IN0
D[3] => SEG[5]~15.IN0
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|LED_7seg_driver:inst|7seg_driver:$00014
D[0] => _.IN0
D[0] => SEG[6]~2.IN3
D[0] => _.IN0
D[0] => SEG[2]~4.IN3
D[0] => _.IN0
D[0] => SEG[5]~6.IN3
D[0] => _.IN0
D[0] => SEG[3]~8.IN3
D[0] => _.IN0
D[0] => SEG[2]~9.IN3
D[0] => _.IN0
D[0] => SEG[6]~11.IN3
D[0] => _.IN0
D[0] => SEG[6]~13.IN3
D[0] => _.IN0
D[0] => SEG[5]~15.IN3
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[4]~3.IN2
D[1] => SEG[2]~4.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~7.IN2
D[1] => SEG[3]~8.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[3]~10.IN2
D[1] => SEG[6]~11.IN2
D[1] => _.IN0
D[1] => _.IN0
D[1] => SEG[5]~14.IN2
D[1] => SEG[5]~15.IN2
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[6]~5.IN1
D[2] => SEG[5]~6.IN1
D[2] => SEG[5]~7.IN1
D[2] => SEG[3]~8.IN1
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => _.IN0
D[2] => SEG[5]~12.IN1
D[2] => SEG[6]~13.IN1
D[2] => SEG[5]~14.IN1
D[2] => SEG[5]~15.IN1
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => _.IN0
D[3] => SEG[2]~9.IN0
D[3] => SEG[3]~10.IN0
D[3] => SEG[6]~11.IN0
D[3] => SEG[5]~12.IN0
D[3] => SEG[6]~13.IN0
D[3] => SEG[5]~14.IN0
D[3] => SEG[5]~15.IN0
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE
|template|test:inst4
test => _.IN0
test => number[0][0].IN0
test => number[1][1].IN0
test => number[2][1].IN0
test => number[2][0].IN0
test => number[3][2].IN0
test => number[4][2].IN0
test => number[4][0].IN0
test => number[5][2].IN0
test => number[5][1].IN0
test => number[6][2].IN0
test => number[6][1].IN0
test => number[6][0].IN0
test => number[7][3].IN0
number[0][0] <= number[0][0].DB_MAX_OUTPUT_PORT_TYPE
number[0][1] <= number[0][1].DB_MAX_OUTPUT_PORT_TYPE
number[0][2] <= number[0][2].DB_MAX_OUTPUT_PORT_TYPE
number[0][3] <= number[0][3].DB_MAX_OUTPUT_PORT_TYPE
number[0][4] <= number[0][4].DB_MAX_OUTPUT_PORT_TYPE
number[1][0] <= number[1][0].DB_MAX_OUTPUT_PORT_TYPE
number[1][1] <= number[1][1].DB_MAX_OUTPUT_PORT_TYPE
number[1][2] <= number[1][2].DB_MAX_OUTPUT_PORT_TYPE
number[1][3] <= number[1][3].DB_MAX_OUTPUT_PORT_TYPE
number[1][4] <= number[1][4].DB_MAX_OUTPUT_PORT_TYPE
number[2][0] <= number[2][0].DB_MAX_OUTPUT_PORT_TYPE
number[2][1] <= number[2][1].DB_MAX_OUTPUT_PORT_TYPE
number[2][2] <= number[2][2].DB_MAX_OUTPUT_PORT_TYPE
number[2][3] <= number[2][3].DB_MAX_OUTPUT_PORT_TYPE
number[2][4] <= number[2][4].DB_MAX_OUTPUT_PORT_TYPE
number[3][0] <= number[3][0].DB_MAX_OUTPUT_PORT_TYPE
number[3][1] <= number[3][1].DB_MAX_OUTPUT_PORT_TYPE
number[3][2] <= number[3][2].DB_MAX_OUTPUT_PORT_TYPE
number[3][3] <= number[3][3].DB_MAX_OUTPUT_PORT_TYPE
number[3][4] <= number[3][4].DB_MAX_OUTPUT_PORT_TYPE
number[4][0] <= number[4][0].DB_MAX_OUTPUT_PORT_TYPE
number[4][1] <= number[4][1].DB_MAX_OUTPUT_PORT_TYPE
number[4][2] <= number[4][2].DB_MAX_OUTPUT_PORT_TYPE
number[4][3] <= number[4][3].DB_MAX_OUTPUT_PORT_TYPE
number[4][4] <= number[4][4].DB_MAX_OUTPUT_PORT_TYPE
number[5][0] <= number[5][0].DB_MAX_OUTPUT_PORT_TYPE
number[5][1] <= number[5][1].DB_MAX_OUTPUT_PORT_TYPE
number[5][2] <= number[5][2].DB_MAX_OUTPUT_PORT_TYPE
number[5][3] <= number[5][3].DB_MAX_OUTPUT_PORT_TYPE
number[5][4] <= number[5][4].DB_MAX_OUTPUT_PORT_TYPE
number[6][0] <= number[6][0].DB_MAX_OUTPUT_PORT_TYPE
number[6][1] <= number[6][1].DB_MAX_OUTPUT_PORT_TYPE
number[6][2] <= number[6][2].DB_MAX_OUTPUT_PORT_TYPE
number[6][3] <= number[6][3].DB_MAX_OUTPUT_PORT_TYPE
number[6][4] <= number[6][4].DB_MAX_OUTPUT_PORT_TYPE
number[7][0] <= number[7][0].DB_MAX_OUTPUT_PORT_TYPE
number[7][1] <= number[7][1].DB_MAX_OUTPUT_PORT_TYPE
number[7][2] <= number[7][2].DB_MAX_OUTPUT_PORT_TYPE
number[7][3] <= number[7][3].DB_MAX_OUTPUT_PORT_TYPE
number[7][4] <= number[7][4].DB_MAX_OUTPUT_PORT_TYPE

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@ -0,0 +1,178 @@
<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >inst4</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >40</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|$00014</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|$00012</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|$00010</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|$00008</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|$00006</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|$00004</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|$00002</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|$00000</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst</TD>
<TD >33</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

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@ -0,0 +1,16 @@
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; inst4 ; 1 ; 0 ; 0 ; 0 ; 40 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst|$00014 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst|$00012 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst|$00010 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst|$00008 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst|$00006 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst|$00004 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst|$00002 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst|$00000 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst ; 33 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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@ -0,0 +1,33 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224927646 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224927646 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:07 2021 " "Processing started: Sat Apr 24 03:42:07 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224927646 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224927646 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224927647 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619224927824 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619224927824 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf " "Can't analyze file -- file ../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1619224934924 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.bdf 1 1 " "Found 1 design units, including 1 entities, in source file template.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 template " "Found entity 1: template" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934926 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934926 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 7 " "Group MSB D7 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 3 " "Group MSB D3 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""}
{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "dig 7 " "Group MSB dig7 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 5 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""}
{ "Warning" "WTDFX_RANGE_CONFLICT" "D 7 0 D 0 7 " "Group is used as \"D\[7..0\]\" and defined using a different range order (\"D\[0..7\]\")" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } } } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""}
{ "Warning" "WTDFX_RANGE_CONFLICT" "D 3 0 D 0 3 " "Group is used as \"D\[3..0\]\" and defined using a different range order (\"D\[0..3\]\")" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } } } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "decoder_out " "Variable or input pin \"decoder_out\" is defined but never used." { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 10 16 0 } } } 0 287013 "Variable or input pin \"%1!s!\" is defined but never used." 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.tdf 1 1 " "Found 1 design units, including 1 entities, in source file template.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 LED_7seg_driver " "Found entity 1: LED_7seg_driver" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934930 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "7seg_driver.tdf 1 1 " "Found 1 design units, including 1 entities, in source file 7seg_driver.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7seg_driver " "Found entity 1: 7seg_driver" { } { { "7seg_driver.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/7seg_driver.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934931 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934931 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.tdf 1 1 " "Found 1 design units, including 1 entities, in source file test.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Found entity 1: test" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934931 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934931 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "template " "Elaborating entity \"template\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619224934975 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_7seg_driver LED_7seg_driver:inst " "Elaborating entity \"LED_7seg_driver\" for hierarchy \"LED_7seg_driver:inst\"" { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934978 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7seg_driver LED_7seg_driver:inst\|7seg_driver:\$00000 " "Elaborating entity \"7seg_driver\" for hierarchy \"LED_7seg_driver:inst\|7seg_driver:\$00000\"" { } { { "template.tdf" "\$00000" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 31 31 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934982 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "test test:inst4 " "Elaborating entity \"test\" for hierarchy \"test:inst4\"" { } { { "template.bdf" "inst4" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 200 64 248 280 "inst4" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934986 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[0\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[0\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[1\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[1\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[2\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[2\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[3\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[3\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[4\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[4\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[5\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[5\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[6\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[6\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WSGN_MISMATCH_PORT" "D\[7\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[7\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[0\] GND " "Pin \"HEX\[0\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[1\] GND " "Pin \"HEX\[1\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[2\] GND " "Pin \"HEX\[2\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[3\] GND " "Pin \"HEX\[3\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[4\] GND " "Pin \"HEX\[4\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[4]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1619224935469 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619224935558 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1619224936053 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224936053 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1619224936080 ""} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Implemented 15 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1619224936080 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1619224936080 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1619224936080 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 22 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:16 2021 " "Processing ended: Sat Apr 24 03:42:16 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224936087 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224942770 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224942771 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:22 2021 " "Processing started: Sat Apr 24 03:42:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224942771 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224942771 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta template -c template " "Command: quartus_sta template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224942771 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1619224942808 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619224942881 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619224942881 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224942949 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224942950 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "template.sdc " "Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619224943126 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943126 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name K\[2\] K\[2\] " "create_clock -period 1.000 -name K\[2\] K\[2\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1619224943127 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943127 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943128 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943128 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619224943129 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619224943132 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1619224943137 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1619224943137 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.356 " "Worst-case setup slack is -0.356" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.356 -0.706 K\[2\] " " -0.356 -0.706 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943138 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.453 " "Worst-case hold slack is 0.453" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.453 0.000 K\[2\] " " 0.453 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943139 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943140 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943140 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -10.435 K\[2\] " " -3.000 -10.435 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943141 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619224943156 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619224943178 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619224943365 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943403 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1619224943404 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1619224943404 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.219 " "Worst-case setup slack is -0.219" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.219 -0.412 K\[2\] " " -0.219 -0.412 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943405 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 K\[2\] " " 0.401 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943406 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943407 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943408 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -10.435 K\[2\] " " -3.000 -10.435 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943409 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619224943425 ""}