diff --git a/AHDL_test/7seg_driver.inc b/AHDL_test/7seg_driver.inc new file mode 100644 index 0000000..d6fcc28 --- /dev/null +++ b/AHDL_test/7seg_driver.inc @@ -0,0 +1,25 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +-- Generated by Quartus Prime Version 20.1 (Build Build 720 11/11/2020) +-- Created on Sat Apr 24 03:39:58 2021 + +FUNCTION 7seg_driver (D[3..0]) + RETURNS (SEG[6..0]); diff --git a/AHDL_test/7seg_driver.tdf b/AHDL_test/7seg_driver.tdf new file mode 100644 index 0000000..3d58198 --- /dev/null +++ b/AHDL_test/7seg_driver.tdf @@ -0,0 +1,23 @@ +subdesign 7seg_driver (D[3..0]: input = VCC; SEG[6..0]: output;) +begin + +case d[] is + when 0 => SEG[6..0] = b"0000001"; + when 1 => SEG[6..0] = b"1001111"; + when 2 => SEG[6..0] = b"0010010"; + when 3 => SEG[6..0] = b"0000110"; + when 4 => SEG[6..0] = b"1001100"; + when 5 => SEG[6..0] = b"0100100"; + when 6 => SEG[6..0] = b"0100000"; + when 7 => SEG[6..0] = b"0001111"; + when 8 => SEG[6..0] = b"0000000"; + when 9 => SEG[6..0] = b"0000100"; + when 10 => SEG[6..0] = b"0001000"; + when 11 => SEG[6..0] = b"1100000"; + when 12 => SEG[6..0] = b"0110001"; + when 13 => SEG[6..0] = b"1000010"; + when 14 => SEG[6..0] = b"0110000"; + when 15 => SEG[6..0] = b"0111000"; + when others => SEG[6..0] = VCC; +end case; +end; \ No newline at end of file diff --git a/AHDL_test/7seg_driver.tdf.bak b/AHDL_test/7seg_driver.tdf.bak new file mode 100644 index 0000000..be2e04c --- /dev/null +++ b/AHDL_test/7seg_driver.tdf.bak @@ -0,0 +1,25 @@ +subdesign 7seg_driver (DP, D[0..3]: input = VCC; SEG[0..7]: output;) +begin + +SEG[7] = DP; + +case d[] is + when 0 => SEG[0..6] = b"0000001"; + when 1 => SEG[0..6] = b"1001111"; + when 2 => SEG[0..6] = b"0010010"; + when 3 => SEG[0..6] = b"0000110"; + when 4 => SEG[0..6] = b"1001100"; + when 5 => SEG[0..6] = b"0100100"; + when 6 => SEG[0..6] = b"0100000"; + when 7 => SEG[0..6] = b"0001111"; + when 8 => SEG[0..6] = b"0000000"; + when 9 => SEG[0..6] = b"0000100"; + when 10 => SEG[0..6] = b"0001000"; + when 11 => SEG[0..6] = b"1100000"; + when 12 => SEG[0..6] = b"0110001"; + when 13 => SEG[0..6] = b"1000010"; + when 14 => SEG[0..6] = b"0110000"; + when 15 => SEG[0..6] = b"0111000"; + when others => SEG[0..6] = VCC; +end case; +end; \ No newline at end of file diff --git a/AHDL_test/LED_7seg_driver.bsf b/AHDL_test/LED_7seg_driver.bsf new file mode 100644 index 0000000..33bc5e4 --- /dev/null +++ b/AHDL_test/LED_7seg_driver.bsf @@ -0,0 +1,58 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 208 96) + (text "LED_7seg_driver" (rect 5 0 79 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "D[0..7][0..4]" (rect 0 0 48 12)(font "Arial" )) + (text "D[0..7][0..4]" (rect 21 27 69 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 43 31 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 192 32) + (output) + (text "dig[0..7]" (rect 0 0 30 12)(font "Arial" )) + (text "dig[0..7]" (rect 141 27 171 39)(font "Arial" )) + (line (pt 192 32)(pt 176 32)(line_width 3)) + ) + (port + (pt 192 48) + (output) + (text "SEG[6..0]" (rect 0 0 40 12)(font "Arial" )) + (text "SEG[6..0]" (rect 131 43 171 55)(font "Arial" )) + (line (pt 192 48)(pt 176 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 176 64)(line_width 1)) + ) +) diff --git a/AHDL_test/db/.cmp.kpt b/AHDL_test/db/.cmp.kpt new file mode 100755 index 0000000..ed4052f Binary files /dev/null and b/AHDL_test/db/.cmp.kpt differ diff --git a/AHDL_test/db/prev_cmp_template.qmsg b/AHDL_test/db/prev_cmp_template.qmsg new file mode 100644 index 0000000..a3bfa19 --- /dev/null +++ b/AHDL_test/db/prev_cmp_template.qmsg @@ -0,0 +1,58 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224882172 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224882172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:41:22 2021 " "Processing started: Sat Apr 24 03:41:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224882172 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224882172 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224882173 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619224882360 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619224882360 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf " "Can't analyze file -- file ../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1619224889452 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.bdf 1 1 " "Found 1 design units, including 1 entities, in source file template.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 template " "Found entity 1: template" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224889453 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889453 ""} +{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 7 " "Group MSB D7 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224889456 ""} +{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 3 " "Group MSB D3 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224889456 ""} +{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "dig 7 " "Group MSB dig7 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 5 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224889456 ""} +{ "Warning" "WTDFX_RANGE_CONFLICT" "D 7 0 D 0 7 " "Group is used as \"D\[7..0\]\" and defined using a different range order (\"D\[0..7\]\")" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } } } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224889457 ""} +{ "Warning" "WTDFX_RANGE_CONFLICT" "D 3 0 D 0 3 " "Group is used as \"D\[3..0\]\" and defined using a different range order (\"D\[0..3\]\")" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } } } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224889457 ""} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "decoder_out " "Variable or input pin \"decoder_out\" is defined but never used." { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 10 16 0 } } } 0 287013 "Variable or input pin \"%1!s!\" is defined but never used." 0 0 "Analysis & Synthesis" 0 -1 1619224889457 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.tdf 1 1 " "Found 1 design units, including 1 entities, in source file template.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 LED_7seg_driver " "Found entity 1: LED_7seg_driver" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224889457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889457 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "7seg_driver.tdf 1 1 " "Found 1 design units, including 1 entities, in source file 7seg_driver.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7seg_driver " "Found entity 1: 7seg_driver" { } { { "7seg_driver.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/7seg_driver.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224889458 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889458 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 8 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number0 " "Symbolic name \"number0\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 8 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 8 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 9 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number1 " "Symbolic name \"number1\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 9 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 9 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 10 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number2 " "Symbolic name \"number2\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 10 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 10 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 11 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number3 " "Symbolic name \"number3\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 11 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 11 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 12 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number4 " "Symbolic name \"number4\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 12 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 12 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 13 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number5 " "Symbolic name \"number5\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 13 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 13 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 14 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number6 " "Symbolic name \"number6\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 14 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 14 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 15 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_UNDEFINED_SYMBOL" "number7 " "Symbolic name \"number7\" is used but not defined" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 15 10 0 } } } 0 287067 "Symbolic name \"%1!s!\" is used but not defined" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 15 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 17 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 17 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 18 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 18 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 19 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 19 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 20 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 20 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 21 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 21 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 22 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 22 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 23 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 23 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889459 ""} +{ "Warning" "WTDFX_NOT_A_1D_ARRAY_WARNING" "number " "Symbolic name \"number\" is used but not defined as a single-range group -- attempted to use existing nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 24 10 0 } } } 0 287020 "Symbolic name \"%1!s!\" is used but not defined as a single-range group -- attempted to use existing nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889460 ""} +{ "Error" "ETDFX_CONSTANT_TO_SCALAR" "" "Numbers cannot be assigned to nodes" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 24 14 0 } } } 0 287113 "Numbers cannot be assigned to nodes" 0 0 "Analysis & Synthesis" 0 -1 1619224889460 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.tdf 0 0 " "Found 0 design units, including 0 entities, in source file test.tdf" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889460 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 24 s 24 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 24 errors, 24 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "354 " "Peak virtual memory: 354 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224889497 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Apr 24 03:41:29 2021 " "Processing ended: Sat Apr 24 03:41:29 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224889497 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224889497 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224889497 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889497 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 26 s 24 s " "Quartus Prime Full Compilation was unsuccessful. 26 errors, 24 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224889604 ""} diff --git a/AHDL_test/db/template.(0).cnf.cdb b/AHDL_test/db/template.(0).cnf.cdb new file mode 100644 index 0000000..cd40387 Binary files /dev/null and b/AHDL_test/db/template.(0).cnf.cdb differ diff --git a/AHDL_test/db/template.(0).cnf.hdb b/AHDL_test/db/template.(0).cnf.hdb new file mode 100644 index 0000000..c9e7d2d Binary files /dev/null and b/AHDL_test/db/template.(0).cnf.hdb differ diff --git a/AHDL_test/db/template.(1).cnf.cdb b/AHDL_test/db/template.(1).cnf.cdb new file mode 100644 index 0000000..0846c08 Binary files /dev/null and b/AHDL_test/db/template.(1).cnf.cdb differ diff --git a/AHDL_test/db/template.(1).cnf.hdb b/AHDL_test/db/template.(1).cnf.hdb new file mode 100644 index 0000000..a985b35 Binary files /dev/null and b/AHDL_test/db/template.(1).cnf.hdb differ diff --git a/AHDL_test/db/template.(2).cnf.cdb b/AHDL_test/db/template.(2).cnf.cdb new file mode 100644 index 0000000..bb7ab43 Binary files /dev/null and b/AHDL_test/db/template.(2).cnf.cdb differ diff --git a/AHDL_test/db/template.(2).cnf.hdb b/AHDL_test/db/template.(2).cnf.hdb new file mode 100644 index 0000000..501e296 Binary files /dev/null and b/AHDL_test/db/template.(2).cnf.hdb differ diff --git a/AHDL_test/db/template.(3).cnf.cdb b/AHDL_test/db/template.(3).cnf.cdb new file mode 100644 index 0000000..8264668 Binary files /dev/null and b/AHDL_test/db/template.(3).cnf.cdb differ diff --git a/AHDL_test/db/template.(3).cnf.hdb b/AHDL_test/db/template.(3).cnf.hdb new file mode 100644 index 0000000..0374f49 Binary files /dev/null and b/AHDL_test/db/template.(3).cnf.hdb differ diff --git a/AHDL_test/db/template.asm.qmsg b/AHDL_test/db/template.asm.qmsg new file mode 100644 index 0000000..17a7041 --- /dev/null +++ b/AHDL_test/db/template.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224941420 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224941421 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:21 2021 " "Processing started: Sat Apr 24 03:42:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224941421 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619224941421 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off template -c template " "Command: quartus_asm --read_settings_files=off --write_settings_files=off template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619224941421 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619224941606 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619224941873 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619224941888 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Peak virtual memory: 351 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:21 2021 " "Processing ended: Sat Apr 24 03:42:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619224941963 ""} diff --git a/AHDL_test/db/template.asm.rdb b/AHDL_test/db/template.asm.rdb new file mode 100644 index 0000000..94c211c Binary files /dev/null and b/AHDL_test/db/template.asm.rdb differ diff --git a/AHDL_test/db/template.asm_labs.ddb b/AHDL_test/db/template.asm_labs.ddb new file mode 100644 index 0000000..8e4a819 Binary files /dev/null and b/AHDL_test/db/template.asm_labs.ddb differ diff --git a/AHDL_test/db/template.cbx.xml b/AHDL_test/db/template.cbx.xml new file mode 100644 index 0000000..15dd418 --- /dev/null +++ b/AHDL_test/db/template.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/AHDL_test/db/template.cmp.bpm b/AHDL_test/db/template.cmp.bpm new file mode 100644 index 0000000..f2e367e Binary files /dev/null and b/AHDL_test/db/template.cmp.bpm differ diff --git a/AHDL_test/db/template.cmp.cdb b/AHDL_test/db/template.cmp.cdb new file mode 100644 index 0000000..95ac548 Binary files /dev/null and b/AHDL_test/db/template.cmp.cdb differ diff --git a/AHDL_test/db/template.cmp.hdb b/AHDL_test/db/template.cmp.hdb new file mode 100644 index 0000000..5d77de3 Binary files /dev/null and b/AHDL_test/db/template.cmp.hdb differ diff --git a/AHDL_test/db/template.cmp.idb b/AHDL_test/db/template.cmp.idb new file mode 100644 index 0000000..6150f44 Binary files /dev/null and b/AHDL_test/db/template.cmp.idb differ diff --git a/AHDL_test/db/template.cmp.logdb b/AHDL_test/db/template.cmp.logdb new file mode 100644 index 0000000..90165e3 --- /dev/null +++ b/AHDL_test/db/template.cmp.logdb @@ -0,0 +1,59 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;17;17;0;0;17;17;0;0;0;0;0;0;15;0;0;0;2;15;0;2;0;0;15;0;17;17;17;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,17;0;0;17;17;0;0;17;17;17;17;17;17;2;17;17;17;15;2;17;15;17;17;2;17;0;0;0;17;17, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,HEX[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,HEX[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SEG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SEG[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SEG[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SEG[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SEG[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SEG[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SEG[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,K[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,K[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/AHDL_test/db/template.cmp.rdb b/AHDL_test/db/template.cmp.rdb new file mode 100644 index 0000000..6d4c798 Binary files /dev/null and b/AHDL_test/db/template.cmp.rdb differ diff --git a/AHDL_test/db/template.cmp_merge.kpt b/AHDL_test/db/template.cmp_merge.kpt new file mode 100644 index 0000000..0252b3f Binary files /dev/null and b/AHDL_test/db/template.cmp_merge.kpt differ diff --git a/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd new file mode 100644 index 0000000..12d57d7 Binary files /dev/null and b/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd b/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd new file mode 100644 index 0000000..16ffdab Binary files /dev/null and b/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd differ diff --git a/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd b/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd new file mode 100644 index 0000000..fb22a11 Binary files /dev/null and b/AHDL_test/db/template.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd differ diff --git a/AHDL_test/db/template.db_info b/AHDL_test/db/template.db_info new file mode 100755 index 0000000..5481b93 --- /dev/null +++ b/AHDL_test/db/template.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Fri Apr 23 19:24:53 2021 diff --git a/AHDL_test/db/template.fit.qmsg b/AHDL_test/db/template.fit.qmsg new file mode 100644 index 0000000..ea1a287 --- /dev/null +++ b/AHDL_test/db/template.fit.qmsg @@ -0,0 +1,47 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1619224936994 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619224936994 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "template EP4CE10E22C8 " "Selected device EP4CE10E22C8 for design \"template\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619224936997 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619224937071 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619224937071 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1619224937187 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619224937191 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6E22C8 " "Device EP4CE6E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619224937231 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619224937231 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1619224937231 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619224937231 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/zen/a-c4e6e10_exemple/AHDL_test/" { { 0 { 0 ""} 0 139 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619224937234 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/zen/a-c4e6e10_exemple/AHDL_test/" { { 0 { 0 ""} 0 141 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619224937234 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/zen/a-c4e6e10_exemple/AHDL_test/" { { 0 { 0 ""} 0 143 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619224937234 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/zen/a-c4e6e10_exemple/AHDL_test/" { { 0 { 0 ""} 0 145 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619224937234 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/zen/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/zen/a-c4e6e10_exemple/AHDL_test/" { { 0 { 0 ""} 0 147 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1619224937234 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1619224937234 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1619224937236 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "template.sdc " "Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1619224937674 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1619224937674 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1619224937677 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1619224937677 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1619224937678 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "K\[2\]~input (placed in PIN 90 (CLK5, DIFFCLK_2n)) " "Automatically promoted node K\[2\]~input (placed in PIN 90 (CLK5, DIFFCLK_2n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1619224937683 ""} } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 296 136 304 312 "K" "" } } } } { "temporary_test_loc" "" { Generic "/home/zen/a-c4e6e10_exemple/AHDL_test/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1619224937683 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1619224937857 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619224937858 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619224937858 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619224937858 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1619224937859 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1619224937859 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1619224937859 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1619224937859 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1619224937860 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1619224937860 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619224937860 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BELL " "Node \"BELL\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "BELL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLK_50M " "Node \"CLK_50M\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLK_50M" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLK_USER " "Node \"CLK_USER\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLK_USER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[10\] " "Node \"D\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[11\] " "Node \"D\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[12\] " "Node \"D\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[13\] " "Node \"D\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[14\] " "Node \"D\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[3\] " "Node \"D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[4\] " "Node \"D\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[5\] " "Node \"D\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[6\] " "Node \"D\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[7\] " "Node \"D\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[8\] " "Node \"D\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "D\[9\] " "Node \"D\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "D\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "K\[4\] " "Node \"K\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "K\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "K\[5\] " "Node \"K\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "K\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_D\[0\] " "Node \"LCD_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_D\[1\] " "Node \"LCD_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_D\[2\] " "Node \"LCD_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_D\[3\] " "Node \"LCD_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_D\[4\] " "Node \"LCD_D\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_D\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_D\[5\] " "Node \"LCD_D\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_D\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_D\[6\] " "Node \"LCD_D\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_D\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_D\[7\] " "Node \"LCD_D\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_D\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_WR " "Node \"LCD_WR\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_WR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "MEM_SCK " "Node \"MEM_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "MEM_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "MEM_SDA " "Node \"MEM_SDA\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "MEM_SDA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS_2_DATA " "Node \"PS_2_DATA\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS_2_DATA" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS_2_SCK " "Node \"PS_2_SCK\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS_2_SCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SEG\[7\] " "Node \"SEG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SEG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RX " "Node \"UART_RX\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RX" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TX " "Node \"UART_TX\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TX" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B " "Node \"VGA_B\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G " "Node \"VGA_G\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R " "Node \"VGA_R\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/zen/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1619224937868 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1619224937868 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619224937869 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1619224937871 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619224938290 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619224938313 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619224938324 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619224938498 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619224938499 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619224938681 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" { } { { "loc" "" { Generic "/home/zen/a-c4e6e10_exemple/AHDL_test/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 12 { 0 ""} 11 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1619224939092 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619224939092 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1619224939259 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1619224939259 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619224939261 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.04 " "Total time spent on timing analysis during the Fitter is 0.04 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1619224939376 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619224939381 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619224939522 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1619224939522 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1619224939659 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619224940021 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1619224940279 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/zen/a-c4e6e10_exemple/AHDL_test/output_files/template.fit.smsg " "Generated suppressed messages file /home/zen/a-c4e6e10_exemple/AHDL_test/output_files/template.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619224940304 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 54 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "942 " "Peak virtual memory: 942 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224940536 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:20 2021 " "Processing ended: Sat Apr 24 03:42:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224940536 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224940536 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224940536 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619224940536 ""} diff --git a/AHDL_test/db/template.hier_info b/AHDL_test/db/template.hier_info new file mode 100644 index 0000000..f3cb200 --- /dev/null +++ b/AHDL_test/db/template.hier_info @@ -0,0 +1,755 @@ +|template +HEX[7] <= LED_7seg_driver:inst.dig[7] +HEX[6] <= LED_7seg_driver:inst.dig[6] +HEX[5] <= LED_7seg_driver:inst.dig[5] +HEX[4] <= LED_7seg_driver:inst.dig[4] +HEX[3] <= LED_7seg_driver:inst.dig[3] +HEX[2] <= LED_7seg_driver:inst.dig[2] +HEX[1] <= LED_7seg_driver:inst.dig[1] +HEX[0] <= LED_7seg_driver:inst.dig[0] +K[2] => LED_7seg_driver:inst.clk +K[3] => test:inst4.test +SEG[6] <= LED_7seg_driver:inst.SEG[0] +SEG[5] <= LED_7seg_driver:inst.SEG[1] +SEG[4] <= LED_7seg_driver:inst.SEG[2] +SEG[3] <= LED_7seg_driver:inst.SEG[3] +SEG[2] <= LED_7seg_driver:inst.SEG[4] +SEG[1] <= LED_7seg_driver:inst.SEG[5] +SEG[0] <= LED_7seg_driver:inst.SEG[6] + + +|template|LED_7seg_driver:inst +D[7][3] => in_buf[7][3].DATAIN +D[7][2] => in_buf[7][2].DATAIN +D[7][1] => in_buf[7][1].DATAIN +D[7][0] => in_buf[7][0].DATAIN +D[6][3] => in_buf[6][3].DATAIN +D[6][2] => in_buf[6][2].DATAIN +D[6][1] => in_buf[6][1].DATAIN +D[6][0] => in_buf[6][0].DATAIN +D[5][3] => in_buf[5][3].DATAIN +D[5][2] => in_buf[5][2].DATAIN +D[5][1] => in_buf[5][1].DATAIN +D[5][0] => in_buf[5][0].DATAIN +D[4][3] => in_buf[4][3].DATAIN +D[4][2] => in_buf[4][2].DATAIN +D[4][1] => in_buf[4][1].DATAIN +D[4][0] => in_buf[4][0].DATAIN +D[3][3] => in_buf[3][3].DATAIN +D[3][2] => in_buf[3][2].DATAIN +D[3][1] => in_buf[3][1].DATAIN +D[3][0] => in_buf[3][0].DATAIN +D[2][3] => in_buf[2][3].DATAIN +D[2][2] => in_buf[2][2].DATAIN +D[2][1] => in_buf[2][1].DATAIN +D[2][0] => in_buf[2][0].DATAIN +D[1][3] => in_buf[1][3].DATAIN +D[1][2] => in_buf[1][2].DATAIN +D[1][1] => in_buf[1][1].DATAIN +D[1][0] => in_buf[1][0].DATAIN +D[0][3] => in_buf[0][3].DATAIN +D[0][2] => in_buf[0][2].DATAIN +D[0][1] => in_buf[0][1].DATAIN +D[0][0] => in_buf[0][0].DATAIN +clk => in_buf[7][3].CLK +clk => in_buf[7][2].CLK +clk => in_buf[7][1].CLK +clk => in_buf[7][0].CLK +clk => in_buf[6][3].CLK +clk => in_buf[6][2].CLK +clk => in_buf[6][1].CLK +clk => in_buf[6][0].CLK +clk => in_buf[5][3].CLK +clk => in_buf[5][2].CLK +clk => in_buf[5][1].CLK +clk => in_buf[5][0].CLK +clk => in_buf[4][3].CLK +clk => in_buf[4][2].CLK +clk => in_buf[4][1].CLK +clk => in_buf[4][0].CLK +clk => in_buf[3][3].CLK +clk => in_buf[3][2].CLK +clk => in_buf[3][1].CLK +clk => in_buf[3][0].CLK +clk => in_buf[2][3].CLK +clk => in_buf[2][2].CLK +clk => in_buf[2][1].CLK +clk => in_buf[2][0].CLK +clk => in_buf[1][3].CLK +clk => in_buf[1][2].CLK +clk => in_buf[1][1].CLK +clk => in_buf[1][0].CLK +clk => in_buf[0][3].CLK +clk => in_buf[0][2].CLK +clk => in_buf[0][1].CLK +clk => in_buf[0][0].CLK +clk => switcher[3].CLK +clk => switcher[2].CLK +clk => switcher[1].CLK +clk => switcher[0].CLK +dig[7] <= dig[7].DB_MAX_OUTPUT_PORT_TYPE +dig[6] <= dig[6].DB_MAX_OUTPUT_PORT_TYPE +dig[5] <= dig[5].DB_MAX_OUTPUT_PORT_TYPE +dig[4] <= dig[4].DB_MAX_OUTPUT_PORT_TYPE +dig[3] <= dig[3].DB_MAX_OUTPUT_PORT_TYPE +dig[2] <= dig[2].DB_MAX_OUTPUT_PORT_TYPE +dig[1] <= dig[1].DB_MAX_OUTPUT_PORT_TYPE +dig[0] <= dig[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|LED_7seg_driver:inst|7seg_driver:$00000 +D[0] => _.IN0 +D[0] => SEG[6]~2.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~4.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~6.IN3 +D[0] => _.IN0 +D[0] => SEG[3]~8.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~9.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~11.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~13.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~15.IN3 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[4]~3.IN2 +D[1] => SEG[2]~4.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~7.IN2 +D[1] => SEG[3]~8.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[3]~10.IN2 +D[1] => SEG[6]~11.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~14.IN2 +D[1] => SEG[5]~15.IN2 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[6]~5.IN1 +D[2] => SEG[5]~6.IN1 +D[2] => SEG[5]~7.IN1 +D[2] => SEG[3]~8.IN1 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[5]~12.IN1 +D[2] => SEG[6]~13.IN1 +D[2] => SEG[5]~14.IN1 +D[2] => SEG[5]~15.IN1 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => SEG[2]~9.IN0 +D[3] => SEG[3]~10.IN0 +D[3] => SEG[6]~11.IN0 +D[3] => SEG[5]~12.IN0 +D[3] => SEG[6]~13.IN0 +D[3] => SEG[5]~14.IN0 +D[3] => SEG[5]~15.IN0 +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|LED_7seg_driver:inst|7seg_driver:$00002 +D[0] => _.IN0 +D[0] => SEG[6]~2.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~4.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~6.IN3 +D[0] => _.IN0 +D[0] => SEG[3]~8.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~9.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~11.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~13.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~15.IN3 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[4]~3.IN2 +D[1] => SEG[2]~4.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~7.IN2 +D[1] => SEG[3]~8.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[3]~10.IN2 +D[1] => SEG[6]~11.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~14.IN2 +D[1] => SEG[5]~15.IN2 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[6]~5.IN1 +D[2] => SEG[5]~6.IN1 +D[2] => SEG[5]~7.IN1 +D[2] => SEG[3]~8.IN1 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[5]~12.IN1 +D[2] => SEG[6]~13.IN1 +D[2] => SEG[5]~14.IN1 +D[2] => SEG[5]~15.IN1 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => SEG[2]~9.IN0 +D[3] => SEG[3]~10.IN0 +D[3] => SEG[6]~11.IN0 +D[3] => SEG[5]~12.IN0 +D[3] => SEG[6]~13.IN0 +D[3] => SEG[5]~14.IN0 +D[3] => SEG[5]~15.IN0 +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|LED_7seg_driver:inst|7seg_driver:$00004 +D[0] => _.IN0 +D[0] => SEG[6]~2.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~4.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~6.IN3 +D[0] => _.IN0 +D[0] => SEG[3]~8.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~9.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~11.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~13.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~15.IN3 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[4]~3.IN2 +D[1] => SEG[2]~4.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~7.IN2 +D[1] => SEG[3]~8.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[3]~10.IN2 +D[1] => SEG[6]~11.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~14.IN2 +D[1] => SEG[5]~15.IN2 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[6]~5.IN1 +D[2] => SEG[5]~6.IN1 +D[2] => SEG[5]~7.IN1 +D[2] => SEG[3]~8.IN1 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[5]~12.IN1 +D[2] => SEG[6]~13.IN1 +D[2] => SEG[5]~14.IN1 +D[2] => SEG[5]~15.IN1 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => SEG[2]~9.IN0 +D[3] => SEG[3]~10.IN0 +D[3] => SEG[6]~11.IN0 +D[3] => SEG[5]~12.IN0 +D[3] => SEG[6]~13.IN0 +D[3] => SEG[5]~14.IN0 +D[3] => SEG[5]~15.IN0 +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|LED_7seg_driver:inst|7seg_driver:$00006 +D[0] => _.IN0 +D[0] => SEG[6]~2.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~4.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~6.IN3 +D[0] => _.IN0 +D[0] => SEG[3]~8.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~9.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~11.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~13.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~15.IN3 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[4]~3.IN2 +D[1] => SEG[2]~4.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~7.IN2 +D[1] => SEG[3]~8.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[3]~10.IN2 +D[1] => SEG[6]~11.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~14.IN2 +D[1] => SEG[5]~15.IN2 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[6]~5.IN1 +D[2] => SEG[5]~6.IN1 +D[2] => SEG[5]~7.IN1 +D[2] => SEG[3]~8.IN1 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[5]~12.IN1 +D[2] => SEG[6]~13.IN1 +D[2] => SEG[5]~14.IN1 +D[2] => SEG[5]~15.IN1 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => SEG[2]~9.IN0 +D[3] => SEG[3]~10.IN0 +D[3] => SEG[6]~11.IN0 +D[3] => SEG[5]~12.IN0 +D[3] => SEG[6]~13.IN0 +D[3] => SEG[5]~14.IN0 +D[3] => SEG[5]~15.IN0 +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|LED_7seg_driver:inst|7seg_driver:$00008 +D[0] => _.IN0 +D[0] => SEG[6]~2.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~4.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~6.IN3 +D[0] => _.IN0 +D[0] => SEG[3]~8.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~9.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~11.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~13.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~15.IN3 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[4]~3.IN2 +D[1] => SEG[2]~4.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~7.IN2 +D[1] => SEG[3]~8.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[3]~10.IN2 +D[1] => SEG[6]~11.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~14.IN2 +D[1] => SEG[5]~15.IN2 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[6]~5.IN1 +D[2] => SEG[5]~6.IN1 +D[2] => SEG[5]~7.IN1 +D[2] => SEG[3]~8.IN1 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[5]~12.IN1 +D[2] => SEG[6]~13.IN1 +D[2] => SEG[5]~14.IN1 +D[2] => SEG[5]~15.IN1 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => SEG[2]~9.IN0 +D[3] => SEG[3]~10.IN0 +D[3] => SEG[6]~11.IN0 +D[3] => SEG[5]~12.IN0 +D[3] => SEG[6]~13.IN0 +D[3] => SEG[5]~14.IN0 +D[3] => SEG[5]~15.IN0 +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|LED_7seg_driver:inst|7seg_driver:$00010 +D[0] => _.IN0 +D[0] => SEG[6]~2.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~4.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~6.IN3 +D[0] => _.IN0 +D[0] => SEG[3]~8.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~9.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~11.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~13.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~15.IN3 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[4]~3.IN2 +D[1] => SEG[2]~4.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~7.IN2 +D[1] => SEG[3]~8.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[3]~10.IN2 +D[1] => SEG[6]~11.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~14.IN2 +D[1] => SEG[5]~15.IN2 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[6]~5.IN1 +D[2] => SEG[5]~6.IN1 +D[2] => SEG[5]~7.IN1 +D[2] => SEG[3]~8.IN1 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[5]~12.IN1 +D[2] => SEG[6]~13.IN1 +D[2] => SEG[5]~14.IN1 +D[2] => SEG[5]~15.IN1 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => SEG[2]~9.IN0 +D[3] => SEG[3]~10.IN0 +D[3] => SEG[6]~11.IN0 +D[3] => SEG[5]~12.IN0 +D[3] => SEG[6]~13.IN0 +D[3] => SEG[5]~14.IN0 +D[3] => SEG[5]~15.IN0 +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|LED_7seg_driver:inst|7seg_driver:$00012 +D[0] => _.IN0 +D[0] => SEG[6]~2.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~4.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~6.IN3 +D[0] => _.IN0 +D[0] => SEG[3]~8.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~9.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~11.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~13.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~15.IN3 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[4]~3.IN2 +D[1] => SEG[2]~4.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~7.IN2 +D[1] => SEG[3]~8.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[3]~10.IN2 +D[1] => SEG[6]~11.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~14.IN2 +D[1] => SEG[5]~15.IN2 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[6]~5.IN1 +D[2] => SEG[5]~6.IN1 +D[2] => SEG[5]~7.IN1 +D[2] => SEG[3]~8.IN1 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[5]~12.IN1 +D[2] => SEG[6]~13.IN1 +D[2] => SEG[5]~14.IN1 +D[2] => SEG[5]~15.IN1 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => SEG[2]~9.IN0 +D[3] => SEG[3]~10.IN0 +D[3] => SEG[6]~11.IN0 +D[3] => SEG[5]~12.IN0 +D[3] => SEG[6]~13.IN0 +D[3] => SEG[5]~14.IN0 +D[3] => SEG[5]~15.IN0 +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|LED_7seg_driver:inst|7seg_driver:$00014 +D[0] => _.IN0 +D[0] => SEG[6]~2.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~4.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~6.IN3 +D[0] => _.IN0 +D[0] => SEG[3]~8.IN3 +D[0] => _.IN0 +D[0] => SEG[2]~9.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~11.IN3 +D[0] => _.IN0 +D[0] => SEG[6]~13.IN3 +D[0] => _.IN0 +D[0] => SEG[5]~15.IN3 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[4]~3.IN2 +D[1] => SEG[2]~4.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~7.IN2 +D[1] => SEG[3]~8.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[3]~10.IN2 +D[1] => SEG[6]~11.IN2 +D[1] => _.IN0 +D[1] => _.IN0 +D[1] => SEG[5]~14.IN2 +D[1] => SEG[5]~15.IN2 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[6]~5.IN1 +D[2] => SEG[5]~6.IN1 +D[2] => SEG[5]~7.IN1 +D[2] => SEG[3]~8.IN1 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => _.IN0 +D[2] => SEG[5]~12.IN1 +D[2] => SEG[6]~13.IN1 +D[2] => SEG[5]~14.IN1 +D[2] => SEG[5]~15.IN1 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => _.IN0 +D[3] => SEG[2]~9.IN0 +D[3] => SEG[3]~10.IN0 +D[3] => SEG[6]~11.IN0 +D[3] => SEG[5]~12.IN0 +D[3] => SEG[6]~13.IN0 +D[3] => SEG[5]~14.IN0 +D[3] => SEG[5]~15.IN0 +SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE +SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE +SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE +SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE +SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE +SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE +SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE + + +|template|test:inst4 +test => _.IN0 +test => number[0][0].IN0 +test => number[1][1].IN0 +test => number[2][1].IN0 +test => number[2][0].IN0 +test => number[3][2].IN0 +test => number[4][2].IN0 +test => number[4][0].IN0 +test => number[5][2].IN0 +test => number[5][1].IN0 +test => number[6][2].IN0 +test => number[6][1].IN0 +test => number[6][0].IN0 +test => number[7][3].IN0 +number[0][0] <= number[0][0].DB_MAX_OUTPUT_PORT_TYPE +number[0][1] <= number[0][1].DB_MAX_OUTPUT_PORT_TYPE +number[0][2] <= number[0][2].DB_MAX_OUTPUT_PORT_TYPE +number[0][3] <= number[0][3].DB_MAX_OUTPUT_PORT_TYPE +number[0][4] <= number[0][4].DB_MAX_OUTPUT_PORT_TYPE +number[1][0] <= number[1][0].DB_MAX_OUTPUT_PORT_TYPE +number[1][1] <= number[1][1].DB_MAX_OUTPUT_PORT_TYPE +number[1][2] <= number[1][2].DB_MAX_OUTPUT_PORT_TYPE +number[1][3] <= number[1][3].DB_MAX_OUTPUT_PORT_TYPE +number[1][4] <= number[1][4].DB_MAX_OUTPUT_PORT_TYPE +number[2][0] <= number[2][0].DB_MAX_OUTPUT_PORT_TYPE +number[2][1] <= number[2][1].DB_MAX_OUTPUT_PORT_TYPE +number[2][2] <= number[2][2].DB_MAX_OUTPUT_PORT_TYPE +number[2][3] <= number[2][3].DB_MAX_OUTPUT_PORT_TYPE +number[2][4] <= number[2][4].DB_MAX_OUTPUT_PORT_TYPE +number[3][0] <= number[3][0].DB_MAX_OUTPUT_PORT_TYPE +number[3][1] <= number[3][1].DB_MAX_OUTPUT_PORT_TYPE +number[3][2] <= number[3][2].DB_MAX_OUTPUT_PORT_TYPE +number[3][3] <= number[3][3].DB_MAX_OUTPUT_PORT_TYPE +number[3][4] <= number[3][4].DB_MAX_OUTPUT_PORT_TYPE +number[4][0] <= number[4][0].DB_MAX_OUTPUT_PORT_TYPE +number[4][1] <= number[4][1].DB_MAX_OUTPUT_PORT_TYPE +number[4][2] <= number[4][2].DB_MAX_OUTPUT_PORT_TYPE +number[4][3] <= number[4][3].DB_MAX_OUTPUT_PORT_TYPE +number[4][4] <= number[4][4].DB_MAX_OUTPUT_PORT_TYPE +number[5][0] <= number[5][0].DB_MAX_OUTPUT_PORT_TYPE +number[5][1] <= number[5][1].DB_MAX_OUTPUT_PORT_TYPE +number[5][2] <= number[5][2].DB_MAX_OUTPUT_PORT_TYPE +number[5][3] <= number[5][3].DB_MAX_OUTPUT_PORT_TYPE +number[5][4] <= number[5][4].DB_MAX_OUTPUT_PORT_TYPE +number[6][0] <= number[6][0].DB_MAX_OUTPUT_PORT_TYPE +number[6][1] <= number[6][1].DB_MAX_OUTPUT_PORT_TYPE +number[6][2] <= number[6][2].DB_MAX_OUTPUT_PORT_TYPE +number[6][3] <= number[6][3].DB_MAX_OUTPUT_PORT_TYPE +number[6][4] <= number[6][4].DB_MAX_OUTPUT_PORT_TYPE +number[7][0] <= number[7][0].DB_MAX_OUTPUT_PORT_TYPE +number[7][1] <= number[7][1].DB_MAX_OUTPUT_PORT_TYPE +number[7][2] <= number[7][2].DB_MAX_OUTPUT_PORT_TYPE +number[7][3] <= number[7][3].DB_MAX_OUTPUT_PORT_TYPE +number[7][4] <= number[7][4].DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/AHDL_test/db/template.hif b/AHDL_test/db/template.hif new file mode 100644 index 0000000..da59711 Binary files /dev/null and b/AHDL_test/db/template.hif differ diff --git a/AHDL_test/db/template.lpc.html b/AHDL_test/db/template.lpc.html new file mode 100644 index 0000000..1bc44c6 --- /dev/null +++ b/AHDL_test/db/template.lpc.html @@ -0,0 +1,178 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
inst410004000000000
inst|$000144000700000000
inst|$000124000700000000
inst|$000104000700000000
inst|$000084000700000000
inst|$000064000700000000
inst|$000044000700000000
inst|$000024000700000000
inst|$000004000700000000
inst330001500000000
diff --git a/AHDL_test/db/template.lpc.rdb b/AHDL_test/db/template.lpc.rdb new file mode 100644 index 0000000..fbd6c4a Binary files /dev/null and b/AHDL_test/db/template.lpc.rdb differ diff --git a/AHDL_test/db/template.lpc.txt b/AHDL_test/db/template.lpc.txt new file mode 100644 index 0000000..429aed4 --- /dev/null +++ b/AHDL_test/db/template.lpc.txt @@ -0,0 +1,16 @@ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; inst4 ; 1 ; 0 ; 0 ; 0 ; 40 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|$00014 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|$00012 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|$00010 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|$00008 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|$00006 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|$00004 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|$00002 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst|$00000 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst ; 33 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/AHDL_test/db/template.map.ammdb b/AHDL_test/db/template.map.ammdb new file mode 100644 index 0000000..790b913 Binary files /dev/null and b/AHDL_test/db/template.map.ammdb differ diff --git a/AHDL_test/db/template.map.bpm b/AHDL_test/db/template.map.bpm new file mode 100644 index 0000000..16396c0 Binary files /dev/null and b/AHDL_test/db/template.map.bpm differ diff --git a/AHDL_test/db/template.map.cdb b/AHDL_test/db/template.map.cdb new file mode 100644 index 0000000..e7a28b8 Binary files /dev/null and b/AHDL_test/db/template.map.cdb differ diff --git a/AHDL_test/db/template.map.hdb b/AHDL_test/db/template.map.hdb new file mode 100644 index 0000000..c624ff0 Binary files /dev/null and b/AHDL_test/db/template.map.hdb differ diff --git a/AHDL_test/db/template.map.kpt b/AHDL_test/db/template.map.kpt new file mode 100644 index 0000000..957832a Binary files /dev/null and b/AHDL_test/db/template.map.kpt differ diff --git a/AHDL_test/db/template.map.logdb b/AHDL_test/db/template.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/AHDL_test/db/template.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/AHDL_test/db/template.map.qmsg b/AHDL_test/db/template.map.qmsg new file mode 100644 index 0000000..f1aa4e6 --- /dev/null +++ b/AHDL_test/db/template.map.qmsg @@ -0,0 +1,33 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224927646 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224927646 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:07 2021 " "Processing started: Sat Apr 24 03:42:07 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224927646 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224927646 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off template -c template " "Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224927647 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1619224927824 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1619224927824 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf " "Can't analyze file -- file ../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1619224934924 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.bdf 1 1 " "Found 1 design units, including 1 entities, in source file template.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 template " "Found entity 1: template" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934926 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934926 ""} +{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 7 " "Group MSB D7 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""} +{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "D 3 " "Group MSB D3 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 4 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""} +{ "Warning" "WTDFX_BIT0_FOUND_AS_MSB" "dig 7 " "Group MSB dig7 overrides BIT0 = LSB in actual or default Options Statement" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 5 5 0 } } } 0 287002 "Group MSB %1!s!%2!d! overrides BIT0 = LSB in actual or default Options Statement" 0 0 "Analysis & Synthesis" 0 -1 1619224934929 ""} +{ "Warning" "WTDFX_RANGE_CONFLICT" "D 7 0 D 0 7 " "Group is used as \"D\[7..0\]\" and defined using a different range order (\"D\[0..7\]\")" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } } } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""} +{ "Warning" "WTDFX_RANGE_CONFLICT" "D 3 0 D 0 3 " "Group is used as \"D\[3..0\]\" and defined using a different range order (\"D\[0..3\]\")" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 20 28 0 } } } 0 287017 "Group is used as \"%1!s!\[%2!d!..%3!d!\]\" and defined using a different range order (\"%4!s!\[%5!d!..%6!d!\]\")" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""} +{ "Warning" "WTDFX_UNREFERENCED_NODE" "decoder_out " "Variable or input pin \"decoder_out\" is defined but never used." { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 10 16 0 } } } 0 287013 "Variable or input pin \"%1!s!\" is defined but never used." 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "template.tdf 1 1 " "Found 1 design units, including 1 entities, in source file template.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 LED_7seg_driver " "Found entity 1: LED_7seg_driver" { } { { "template.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 3 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934930 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934930 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "7seg_driver.tdf 1 1 " "Found 1 design units, including 1 entities, in source file 7seg_driver.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 7seg_driver " "Found entity 1: 7seg_driver" { } { { "7seg_driver.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/7seg_driver.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934931 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934931 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.tdf 1 1 " "Found 1 design units, including 1 entities, in source file test.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Found entity 1: test" { } { { "test.tdf" "" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf" 1 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1619224934931 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224934931 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "template " "Elaborating entity \"template\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1619224934975 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED_7seg_driver LED_7seg_driver:inst " "Elaborating entity \"LED_7seg_driver\" for hierarchy \"LED_7seg_driver:inst\"" { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934978 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7seg_driver LED_7seg_driver:inst\|7seg_driver:\$00000 " "Elaborating entity \"7seg_driver\" for hierarchy \"LED_7seg_driver:inst\|7seg_driver:\$00000\"" { } { { "template.tdf" "\$00000" { Text "/home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf" 31 31 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934982 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "test test:inst4 " "Elaborating entity \"test\" for hierarchy \"test:inst4\"" { } { { "template.bdf" "inst4" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 200 64 248 280 "inst4" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224934986 ""} +{ "Warning" "WSGN_MISMATCH_PORT" "D\[0\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[0\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""} +{ "Warning" "WSGN_MISMATCH_PORT" "D\[1\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[1\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""} +{ "Warning" "WSGN_MISMATCH_PORT" "D\[2\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[2\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""} +{ "Warning" "WSGN_MISMATCH_PORT" "D\[3\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[3\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""} +{ "Warning" "WSGN_MISMATCH_PORT" "D\[4\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[4\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""} +{ "Warning" "WSGN_MISMATCH_PORT" "D\[5\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[5\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""} +{ "Warning" "WSGN_MISMATCH_PORT" "D\[6\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[6\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""} +{ "Warning" "WSGN_MISMATCH_PORT" "D\[7\]\[4\] LED_7seg_driver LED_7seg_driver:inst " "Port \"D\[7\]\[4\]\" does not exist in entity definition of \"LED_7seg_driver\". The port's range differs between the entity definition and its actual instantiation, \"LED_7seg_driver:inst\"." { } { { "template.bdf" "inst" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 256 304 496 336 "inst" "" } } } } } 0 12001 "Port \"%1!s!\" does not exist in entity definition of \"%2!s!\". The port's range differs between the entity definition and its actual instantiation, \"%3!s!\"." 0 0 "Analysis & Synthesis" 0 -1 1619224934998 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[0\] GND " "Pin \"HEX\[0\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[1\] GND " "Pin \"HEX\[1\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[2\] GND " "Pin \"HEX\[2\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[3\] GND " "Pin \"HEX\[3\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX\[4\] GND " "Pin \"HEX\[4\]\" is stuck at GND" { } { { "template.bdf" "" { Schematic "/home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf" { { 280 496 672 296 "HEX\[0..7\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1619224935469 "|template|HEX[4]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1619224935469 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1619224935558 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1619224936053 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1619224936053 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "33 " "Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1619224936080 ""} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Implemented 15 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1619224936080 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1619224936080 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1619224936080 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 22 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:16 2021 " "Processing ended: Sat Apr 24 03:42:16 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224936087 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1619224936087 ""} diff --git a/AHDL_test/db/template.map.rdb b/AHDL_test/db/template.map.rdb new file mode 100644 index 0000000..d56dee4 Binary files /dev/null and b/AHDL_test/db/template.map.rdb differ diff --git a/AHDL_test/db/template.map_bb.cdb b/AHDL_test/db/template.map_bb.cdb new file mode 100644 index 0000000..b842d2b Binary files /dev/null and b/AHDL_test/db/template.map_bb.cdb differ diff --git a/AHDL_test/db/template.map_bb.hdb b/AHDL_test/db/template.map_bb.hdb new file mode 100644 index 0000000..e8ba5a3 Binary files /dev/null and b/AHDL_test/db/template.map_bb.hdb differ diff --git a/AHDL_test/db/template.map_bb.logdb b/AHDL_test/db/template.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/AHDL_test/db/template.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/AHDL_test/db/template.pplq.rdb b/AHDL_test/db/template.pplq.rdb new file mode 100644 index 0000000..8a7c26e Binary files /dev/null and b/AHDL_test/db/template.pplq.rdb differ diff --git a/AHDL_test/db/template.pre_map.hdb b/AHDL_test/db/template.pre_map.hdb new file mode 100644 index 0000000..d41bc83 Binary files /dev/null and b/AHDL_test/db/template.pre_map.hdb differ diff --git a/AHDL_test/db/template.root_partition.map.reg_db.cdb b/AHDL_test/db/template.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..13b2cd2 Binary files /dev/null and b/AHDL_test/db/template.root_partition.map.reg_db.cdb differ diff --git a/AHDL_test/db/template.routing.rdb b/AHDL_test/db/template.routing.rdb new file mode 100644 index 0000000..8ea37ef Binary files /dev/null and b/AHDL_test/db/template.routing.rdb differ diff --git a/AHDL_test/db/template.rtlv.hdb b/AHDL_test/db/template.rtlv.hdb new file mode 100644 index 0000000..1ce591c Binary files /dev/null and b/AHDL_test/db/template.rtlv.hdb differ diff --git a/AHDL_test/db/template.rtlv_sg.cdb b/AHDL_test/db/template.rtlv_sg.cdb new file mode 100644 index 0000000..87b07ee Binary files /dev/null and b/AHDL_test/db/template.rtlv_sg.cdb differ diff --git a/AHDL_test/db/template.rtlv_sg_swap.cdb b/AHDL_test/db/template.rtlv_sg_swap.cdb new file mode 100644 index 0000000..f3be8bc Binary files /dev/null and b/AHDL_test/db/template.rtlv_sg_swap.cdb differ diff --git a/AHDL_test/db/template.sld_design_entry.sci b/AHDL_test/db/template.sld_design_entry.sci new file mode 100644 index 0000000..7d39add Binary files /dev/null and b/AHDL_test/db/template.sld_design_entry.sci differ diff --git a/AHDL_test/db/template.sld_design_entry_dsc.sci b/AHDL_test/db/template.sld_design_entry_dsc.sci new file mode 100644 index 0000000..7d39add Binary files /dev/null and b/AHDL_test/db/template.sld_design_entry_dsc.sci differ diff --git a/AHDL_test/db/template.smart_action.txt b/AHDL_test/db/template.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/AHDL_test/db/template.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/AHDL_test/db/template.sta.qmsg b/AHDL_test/db/template.sta.qmsg new file mode 100644 index 0000000..ec5bdb2 --- /dev/null +++ b/AHDL_test/db/template.sta.qmsg @@ -0,0 +1,42 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224942770 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224942771 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:22 2021 " "Processing started: Sat Apr 24 03:42:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224942771 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224942771 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta template -c template " "Command: quartus_sta template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224942771 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1619224942808 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619224942881 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619224942881 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224942949 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224942950 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "template.sdc " "Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619224943126 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943126 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name K\[2\] K\[2\] " "create_clock -period 1.000 -name K\[2\] K\[2\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1619224943127 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943127 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943128 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943128 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619224943129 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619224943132 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1619224943137 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1619224943137 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.356 " "Worst-case setup slack is -0.356" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.356 -0.706 K\[2\] " " -0.356 -0.706 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943138 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.453 " "Worst-case hold slack is 0.453" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.453 0.000 K\[2\] " " 0.453 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943139 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943140 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943140 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -10.435 K\[2\] " " -3.000 -10.435 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943141 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619224943156 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619224943178 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619224943365 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943403 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1619224943404 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1619224943404 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.219 " "Worst-case setup slack is -0.219" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.219 -0.412 K\[2\] " " -0.219 -0.412 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943405 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 K\[2\] " " 0.401 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943406 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943407 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943408 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -10.435 K\[2\] " " -3.000 -10.435 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943409 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619224943425 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943553 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.404 " "Worst-case setup slack is 0.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.404 0.000 K\[2\] " " 0.404 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943554 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943554 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.187 " "Worst-case hold slack is 0.187" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.187 0.000 K\[2\] " " 0.187 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943556 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943556 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943557 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943558 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1619224943558 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1619224943558 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -8.315 K\[2\] " " -3.000 -8.315 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943559 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943559 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619224943937 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619224943937 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "444 " "Peak virtual memory: 444 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224943955 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:23 2021 " "Processing ended: Sat Apr 24 03:42:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224943955 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224943955 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224943955 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619224943955 ""} diff --git a/AHDL_test/db/template.sta.rdb b/AHDL_test/db/template.sta.rdb new file mode 100644 index 0000000..0f665a3 Binary files /dev/null and b/AHDL_test/db/template.sta.rdb differ diff --git a/AHDL_test/db/template.sta_cmp.8_slow_1200mv_85c.tdb b/AHDL_test/db/template.sta_cmp.8_slow_1200mv_85c.tdb new file mode 100644 index 0000000..a35b0d2 Binary files /dev/null and b/AHDL_test/db/template.sta_cmp.8_slow_1200mv_85c.tdb differ diff --git a/AHDL_test/db/template.tis_db_list.ddb b/AHDL_test/db/template.tis_db_list.ddb new file mode 100644 index 0000000..abcfeea Binary files /dev/null and b/AHDL_test/db/template.tis_db_list.ddb differ diff --git a/AHDL_test/db/template.tiscmp.fast_1200mv_0c.ddb b/AHDL_test/db/template.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..dbcdeb6 Binary files /dev/null and b/AHDL_test/db/template.tiscmp.fast_1200mv_0c.ddb differ diff --git a/AHDL_test/db/template.tiscmp.fastest_slow_1200mv_0c.ddb b/AHDL_test/db/template.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..3594414 Binary files /dev/null and b/AHDL_test/db/template.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/AHDL_test/db/template.tiscmp.fastest_slow_1200mv_85c.ddb b/AHDL_test/db/template.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..b1ca6a5 Binary files /dev/null and b/AHDL_test/db/template.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/AHDL_test/db/template.tiscmp.slow_1200mv_0c.ddb b/AHDL_test/db/template.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..2144532 Binary files /dev/null and b/AHDL_test/db/template.tiscmp.slow_1200mv_0c.ddb differ diff --git a/AHDL_test/db/template.tiscmp.slow_1200mv_85c.ddb b/AHDL_test/db/template.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..a546274 Binary files /dev/null and b/AHDL_test/db/template.tiscmp.slow_1200mv_85c.ddb differ diff --git a/AHDL_test/db/template.tmw_info b/AHDL_test/db/template.tmw_info new file mode 100644 index 0000000..0470e76 --- /dev/null +++ b/AHDL_test/db/template.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:18 +start_analysis_synthesis:s:00:00:10-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:04-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation diff --git a/AHDL_test/db/template.vpr.ammdb b/AHDL_test/db/template.vpr.ammdb new file mode 100644 index 0000000..b75e8d8 Binary files /dev/null and b/AHDL_test/db/template.vpr.ammdb differ diff --git a/AHDL_test/db/template_partition_pins.json b/AHDL_test/db/template_partition_pins.json new file mode 100644 index 0000000..83d0d61 --- /dev/null +++ b/AHDL_test/db/template_partition_pins.json @@ -0,0 +1,57 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "HEX[5]", + "strict" : false + }, + { + "name" : "HEX[6]", + "strict" : false + }, + { + "name" : "HEX[7]", + "strict" : false + }, + { + "name" : "SEG[0]", + "strict" : false + }, + { + "name" : "SEG[1]", + "strict" : false + }, + { + "name" : "SEG[2]", + "strict" : false + }, + { + "name" : "SEG[3]", + "strict" : false + }, + { + "name" : "SEG[4]", + "strict" : false + }, + { + "name" : "SEG[5]", + "strict" : false + }, + { + "name" : "SEG[6]", + "strict" : false + }, + { + "name" : "K[2]", + "strict" : false + }, + { + "name" : "K[3]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/AHDL_test/incremental_db/README b/AHDL_test/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/AHDL_test/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/AHDL_test/incremental_db/compiled_partitions/template.db_info b/AHDL_test/incremental_db/compiled_partitions/template.db_info new file mode 100644 index 0000000..3b951c5 --- /dev/null +++ b/AHDL_test/incremental_db/compiled_partitions/template.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Fri Apr 23 19:27:34 2021 diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.ammdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.ammdb new file mode 100644 index 0000000..bdaff60 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.ammdb differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.cdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.cdb new file mode 100644 index 0000000..a3de58c Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.cdb differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.dfp b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.dfp differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.hdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.hdb new file mode 100644 index 0000000..51973b8 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.hdb differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.logdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.rcfdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.rcfdb new file mode 100644 index 0000000..0ccff94 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.cmp.rcfdb differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.cdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.cdb new file mode 100644 index 0000000..6364c41 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.cdb differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.dpi b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.dpi new file mode 100644 index 0000000..0ee657b Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.dpi differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.cdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..1f4c9f1 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.cdb differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.hb_info b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.hb_info differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.hdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..0418828 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.hdb differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.sig b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.sig new file mode 100644 index 0000000..6c0af65 --- /dev/null +++ b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +c5eb7f6cdd530884c3b884e0a3668ea4 \ No newline at end of file diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hdb b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hdb new file mode 100644 index 0000000..01eb588 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.hdb differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.kpt b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.kpt new file mode 100644 index 0000000..b17b6cf Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.root_partition.map.kpt differ diff --git a/AHDL_test/incremental_db/compiled_partitions/template.rrp.hdb b/AHDL_test/incremental_db/compiled_partitions/template.rrp.hdb new file mode 100644 index 0000000..5ed69f4 Binary files /dev/null and b/AHDL_test/incremental_db/compiled_partitions/template.rrp.hdb differ diff --git a/AHDL_test/output_files/template.asm.rpt b/AHDL_test/output_files/template.asm.rpt new file mode 100644 index 0000000..79af42d --- /dev/null +++ b/AHDL_test/output_files/template.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for template +Sat Apr 24 03:42:21 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: template.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Apr 24 03:42:21 2021 ; +; Revision Name ; template ; +; Top-level Entity Name ; template ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10E22C8 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------+ +; /home/zen/a-c4e6e10_exemple/AHDL_test/output_files/template.sof ; ++-----------------------------------------------------------------+ + + ++----------------------------------------+ +; Assembler Device Options: template.sof ; ++----------------+-----------------------+ +; Option ; Setting ; ++----------------+-----------------------+ +; JTAG usercode ; 0x00095D12 ; +; Checksum ; 0x00095D12 ; ++----------------+-----------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 03:42:21 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off template -c template +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 351 megabytes + Info: Processing ended: Sat Apr 24 03:42:21 2021 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/AHDL_test/output_files/template.done b/AHDL_test/output_files/template.done new file mode 100755 index 0000000..cdd0897 --- /dev/null +++ b/AHDL_test/output_files/template.done @@ -0,0 +1 @@ +Sat Apr 24 03:42:24 2021 diff --git a/AHDL_test/output_files/template.fit.rpt b/AHDL_test/output_files/template.fit.rpt new file mode 100644 index 0000000..4b12f8d --- /dev/null +++ b/AHDL_test/output_files/template.fit.rpt @@ -0,0 +1,1041 @@ +Fitter report for template +Sat Apr 24 03:42:20 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Control Signals + 22. Global & Other Fast Signals + 23. Routing Usage Summary + 24. LAB Logic Elements + 25. LAB-wide Signals + 26. LAB Signals Sourced + 27. LAB Signals Sourced Out + 28. LAB Distinct Inputs + 29. I/O Rules Summary + 30. I/O Rules Details + 31. I/O Rules Matrix + 32. Fitter Device Options + 33. Operating Settings and Conditions + 34. Fitter Messages + 35. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sat Apr 24 03:42:20 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; template ; +; Top-level Entity Name ; template ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10E22C8 ; +; Timing Models ; Final ; +; Total logic elements ; 16 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 15 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 5 / 10,320 ( < 1 % ) ; +; Total registers ; 5 ; +; Total pins ; 17 / 92 ( 18 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP4CE10E22C8 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.2% ; +; Processors 3-4 ; 0.2% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; BELL ; PIN_141 ; QSF Assignment ; +; Location ; ; ; CLK_50M ; PIN_23 ; QSF Assignment ; +; Location ; ; ; CLK_USER ; PIN_24 ; QSF Assignment ; +; Location ; ; ; D[10] ; PIN_76 ; QSF Assignment ; +; Location ; ; ; D[11] ; PIN_75 ; QSF Assignment ; +; Location ; ; ; D[12] ; PIN_71 ; QSF Assignment ; +; Location ; ; ; D[13] ; PIN_70 ; QSF Assignment ; +; Location ; ; ; D[14] ; PIN_69 ; QSF Assignment ; +; Location ; ; ; D[3] ; PIN_72 ; QSF Assignment ; +; Location ; ; ; D[4] ; PIN_73 ; QSF Assignment ; +; Location ; ; ; D[5] ; PIN_74 ; QSF Assignment ; +; Location ; ; ; D[6] ; PIN_80 ; QSF Assignment ; +; Location ; ; ; D[7] ; PIN_83 ; QSF Assignment ; +; Location ; ; ; D[8] ; PIN_84 ; QSF Assignment ; +; Location ; ; ; D[9] ; PIN_77 ; QSF Assignment ; +; Location ; ; ; K[4] ; PIN_87 ; QSF Assignment ; +; Location ; ; ; K[5] ; PIN_86 ; QSF Assignment ; +; Location ; ; ; LCD_D[0] ; PIN_101 ; QSF Assignment ; +; Location ; ; ; LCD_D[1] ; PIN_103 ; QSF Assignment ; +; Location ; ; ; LCD_D[2] ; PIN_104 ; QSF Assignment ; +; Location ; ; ; LCD_D[3] ; PIN_105 ; QSF Assignment ; +; Location ; ; ; LCD_D[4] ; PIN_106 ; QSF Assignment ; +; Location ; ; ; LCD_D[5] ; PIN_110 ; QSF Assignment ; +; Location ; ; ; LCD_D[6] ; PIN_111 ; QSF Assignment ; +; Location ; ; ; LCD_D[7] ; PIN_112 ; QSF Assignment ; +; Location ; ; ; LCD_EN ; PIN_100 ; QSF Assignment ; +; Location ; ; ; LCD_RS ; PIN_85 ; QSF Assignment ; +; Location ; ; ; LCD_WR ; PIN_99 ; QSF Assignment ; +; Location ; ; ; MEM_SCK ; PIN_7 ; QSF Assignment ; +; Location ; ; ; MEM_SDA ; PIN_3 ; QSF Assignment ; +; Location ; ; ; PS_2_DATA ; PIN_10 ; QSF Assignment ; +; Location ; ; ; PS_2_SCK ; PIN_11 ; QSF Assignment ; +; Location ; ; ; SEG[7] ; PIN_115 ; QSF Assignment ; +; Location ; ; ; SW[1] ; PIN_58 ; QSF Assignment ; +; Location ; ; ; SW[2] ; PIN_59 ; QSF Assignment ; +; Location ; ; ; SW[3] ; PIN_60 ; QSF Assignment ; +; Location ; ; ; SW[4] ; PIN_64 ; QSF Assignment ; +; Location ; ; ; SW[5] ; PIN_65 ; QSF Assignment ; +; Location ; ; ; SW[6] ; PIN_66 ; QSF Assignment ; +; Location ; ; ; SW[7] ; PIN_67 ; QSF Assignment ; +; Location ; ; ; SW[8] ; PIN_68 ; QSF Assignment ; +; Location ; ; ; UART_RX ; PIN_113 ; QSF Assignment ; +; Location ; ; ; UART_TX ; PIN_114 ; QSF Assignment ; +; Location ; ; ; VGA_B ; PIN_144 ; QSF Assignment ; +; Location ; ; ; VGA_G ; PIN_1 ; QSF Assignment ; +; Location ; ; ; VGA_HS ; PIN_142 ; QSF Assignment ; +; Location ; ; ; VGA_R ; PIN_2 ; QSF Assignment ; +; Location ; ; ; VGA_VS ; PIN_143 ; QSF Assignment ; ++----------+----------------+--------------+------------+---------------+----------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 66 ) ; 0.00 % ( 0 / 66 ) ; 0.00 % ( 0 / 66 ) ; +; -- Achieved ; 0.00 % ( 0 / 66 ) ; 0.00 % ( 0 / 66 ) ; 0.00 % ( 0 / 66 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 56 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/zen/a-c4e6e10_exemple/AHDL_test/output_files/template.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 16 / 10,320 ( < 1 % ) ; +; -- Combinational with no register ; 11 ; +; -- Register only ; 1 ; +; -- Combinational with a register ; 4 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 3 ; +; -- 3 input functions ; 6 ; +; -- <=2 input functions ; 6 ; +; -- Register only ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 15 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 5 / 10,732 ( < 1 % ) ; +; -- Dedicated logic registers ; 5 / 10,320 ( < 1 % ) ; +; -- I/O registers ; 0 / 412 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 645 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 17 / 92 ( 18 % ) ; +; -- Clock pins ; 1 / 3 ( 33 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; M9Ks ; 0 / 46 ( 0 % ) ; +; Total block memory bits ; 0 / 423,936 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global signals ; 1 ; +; -- Global clocks ; 1 / 10 ( 10 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.1% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.1% ; +; Maximum fan-out ; 10 ; +; Highest non-global fan-out ; 10 ; +; Total fan-out ; 84 ; +; Average fan-out ; 1.29 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 16 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- Combinational with no register ; 11 ; 0 ; +; -- Register only ; 1 ; 0 ; +; -- Combinational with a register ; 4 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 3 ; 0 ; +; -- 3 input functions ; 6 ; 0 ; +; -- <=2 input functions ; 6 ; 0 ; +; -- Register only ; 1 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 15 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 5 ; 0 ; +; -- Dedicated logic registers ; 5 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 645 ( < 1 % ) ; 0 / 645 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 17 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; 0 / 46 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; Clock control block ; 1 / 12 ( 8 % ) ; 0 / 12 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 79 ; 5 ; +; -- Registered Connections ; 36 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 2 ; 0 ; +; -- Output Ports ; 15 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; K[2] ; 90 ; 6 ; 34 ; 12 ; 7 ; 5 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ; +; K[3] ; 91 ; 6 ; 34 ; 12 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; HEX[0] ; 128 ; 8 ; 16 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX[1] ; 129 ; 8 ; 16 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX[2] ; 132 ; 8 ; 13 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX[3] ; 133 ; 8 ; 13 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX[4] ; 135 ; 8 ; 11 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX[5] ; 136 ; 8 ; 9 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX[6] ; 137 ; 8 ; 7 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX[7] ; 138 ; 8 ; 7 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; SEG[0] ; 127 ; 7 ; 16 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; SEG[1] ; 126 ; 7 ; 16 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; SEG[2] ; 125 ; 7 ; 18 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; SEG[3] ; 124 ; 7 ; 18 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; SEG[4] ; 121 ; 7 ; 23 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; SEG[5] ; 120 ; 7 ; 23 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; SEG[6] ; 119 ; 7 ; 23 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++--------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; 6 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; 8 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; 9 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; 12 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; 13 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; 14 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; 21 ; nCE ; - ; - ; Dedicated Programming Pin ; +; 92 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; 94 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; 96 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; 97 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; 97 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; 101 ; DIFFIO_R3n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; 132 ; DIFFIO_T10n, DATA2 ; Use as regular IO ; HEX[2] ; Dual Purpose Pin ; +; 133 ; DIFFIO_T10p, DATA3 ; Use as regular IO ; HEX[3] ; Dual Purpose Pin ; +; 137 ; DATA5 ; Use as regular IO ; HEX[6] ; Dual Purpose Pin ; +; 138 ; DATA6 ; Use as regular IO ; HEX[7] ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1 ; 4 / 11 ( 36 % ) ; 2.5V ; -- ; +; 2 ; 0 / 8 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 11 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 3 / 10 ( 30 % ) ; 2.5V ; -- ; +; 7 ; 7 / 13 ( 54 % ) ; 2.5V ; -- ; +; 8 ; 8 / 12 ( 67 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 3 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 6 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 7 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 8 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 9 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; 10 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 11 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 12 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 13 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 14 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; 15 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 16 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 17 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 18 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 20 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 21 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; 22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 23 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 24 ; 25 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 25 ; 26 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 26 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 28 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 29 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 30 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 31 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 32 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 33 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 34 ; 41 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 35 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 36 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 37 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 38 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 39 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 40 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 41 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 42 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 43 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 44 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 45 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 46 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 47 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 48 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 49 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 50 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 51 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 52 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 53 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 54 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 55 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 56 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 57 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 58 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 59 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 60 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 61 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 62 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 63 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 64 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 65 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 66 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 67 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 68 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 69 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 70 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 71 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 72 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 73 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 74 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 75 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 76 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 77 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 78 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 81 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 82 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 83 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 84 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 85 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 86 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 87 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 88 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 89 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 90 ; 127 ; 6 ; K[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; 91 ; 128 ; 6 ; K[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; 92 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; 93 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 94 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; 95 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 96 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; 97 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; 97 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; 98 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 99 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 100 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 101 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 102 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 103 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 104 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 105 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 106 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 107 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 108 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 109 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 110 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 111 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 112 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 113 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 114 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 115 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 116 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 117 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 118 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 119 ; 163 ; 7 ; SEG[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 120 ; 164 ; 7 ; SEG[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 121 ; 165 ; 7 ; SEG[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 122 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 123 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 124 ; 173 ; 7 ; SEG[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 125 ; 174 ; 7 ; SEG[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 126 ; 175 ; 7 ; SEG[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 127 ; 176 ; 7 ; SEG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 128 ; 177 ; 8 ; HEX[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 129 ; 178 ; 8 ; HEX[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 130 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 131 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 132 ; 181 ; 8 ; HEX[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 133 ; 182 ; 8 ; HEX[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 134 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 135 ; 185 ; 8 ; HEX[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 136 ; 187 ; 8 ; HEX[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 137 ; 190 ; 8 ; HEX[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 138 ; 191 ; 8 ; HEX[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; 139 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 141 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 142 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 143 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 144 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; EPAD ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; HEX[0] ; Incomplete set of assignments ; +; HEX[1] ; Incomplete set of assignments ; +; HEX[2] ; Incomplete set of assignments ; +; HEX[3] ; Incomplete set of assignments ; +; HEX[4] ; Incomplete set of assignments ; +; HEX[5] ; Incomplete set of assignments ; +; HEX[6] ; Incomplete set of assignments ; +; HEX[7] ; Incomplete set of assignments ; +; SEG[0] ; Incomplete set of assignments ; +; SEG[1] ; Incomplete set of assignments ; +; SEG[2] ; Incomplete set of assignments ; +; SEG[3] ; Incomplete set of assignments ; +; SEG[4] ; Incomplete set of assignments ; +; SEG[5] ; Incomplete set of assignments ; +; SEG[6] ; Incomplete set of assignments ; +; K[2] ; Incomplete set of assignments ; +; K[3] ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+-----------------+--------------+ +; |template ; 16 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; 11 (0) ; 1 (0) ; 4 (0) ; |template ; template ; work ; +; |LED_7seg_driver:inst| ; 16 (16) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 1 (1) ; 4 (4) ; |template|LED_7seg_driver:inst ; LED_7seg_driver ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++--------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++--------+----------+---------------+---------------+-----------------------+-----+------+ +; HEX[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SEG[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SEG[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SEG[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SEG[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SEG[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SEG[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; SEG[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; K[2] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; K[3] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; ++--------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; K[2] ; ; ; +; K[3] ; ; ; ++---------------------+-------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+ +; K[2] ; PIN_90 ; 5 ; Clock ; yes ; Global Clock ; GCLK7 ; -- ; ++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; K[2] ; PIN_90 ; 5 ; 0 ; Global Clock ; GCLK7 ; -- ; ++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-----------------------+ +; Block interconnects ; 19 / 32,401 ( < 1 % ) ; +; C16 interconnects ; 1 / 1,326 ( < 1 % ) ; +; C4 interconnects ; 10 / 21,816 ( < 1 % ) ; +; Direct links ; 8 / 32,401 ( < 1 % ) ; +; Global clocks ; 1 / 10 ( 10 % ) ; +; Local interconnects ; 6 / 10,320 ( < 1 % ) ; +; R24 interconnects ; 1 / 1,289 ( < 1 % ) ; +; R4 interconnects ; 13 / 28,186 ( < 1 % ) ; ++-----------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 2) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 0.50) ; Number of LABs (Total = 2) ; ++------------------------------------+-----------------------------+ +; 1 Clock ; 1 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 10.00) ; Number of LABs (Total = 2) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.50) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 2.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 17 ; 17 ; 0 ; 0 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 2 ; 15 ; 0 ; 2 ; 0 ; 0 ; 15 ; 0 ; 17 ; 17 ; 17 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 17 ; 0 ; 0 ; 17 ; 17 ; 0 ; 0 ; 17 ; 17 ; 17 ; 17 ; 17 ; 17 ; 2 ; 17 ; 17 ; 17 ; 15 ; 2 ; 17 ; 15 ; 17 ; 17 ; 2 ; 17 ; 0 ; 0 ; 0 ; 17 ; 17 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; HEX[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; HEX[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SEG[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SEG[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SEG[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SEG[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SEG[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SEG[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; SEG[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; K[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; K[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EP4CE10E22C8 for design "template" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE6E22C8 is compatible + Info (176445): Device EP4CE15E22C8 is compatible + Info (176445): Device EP4CE22E22C8 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node K[2]~input (placed in PIN 90 (CLK5, DIFFCLK_2n)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "BELL" is assigned to location or region, but does not exist in design + Warning (15706): Node "CLK_50M" is assigned to location or region, but does not exist in design + Warning (15706): Node "CLK_USER" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "D[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "K[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "K[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_D[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_D[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_D[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_D[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_D[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_D[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_D[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_D[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design + Warning (15706): Node "LCD_WR" is assigned to location or region, but does not exist in design + Warning (15706): Node "MEM_SCK" is assigned to location or region, but does not exist in design + Warning (15706): Node "MEM_SDA" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS_2_DATA" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS_2_SCK" is assigned to location or region, but does not exist in design + Warning (15706): Node "SEG[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "UART_RX" is assigned to location or region, but does not exist in design + Warning (15706): Node "UART_TX" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file /home/zen/a-c4e6e10_exemple/AHDL_test/output_files/template.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 54 warnings + Info: Peak virtual memory: 942 megabytes + Info: Processing ended: Sat Apr 24 03:42:20 2021 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:05 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/zen/a-c4e6e10_exemple/AHDL_test/output_files/template.fit.smsg. + + diff --git a/AHDL_test/output_files/template.fit.smsg b/AHDL_test/output_files/template.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/AHDL_test/output_files/template.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/AHDL_test/output_files/template.fit.summary b/AHDL_test/output_files/template.fit.summary new file mode 100755 index 0000000..95a8e35 --- /dev/null +++ b/AHDL_test/output_files/template.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Sat Apr 24 03:42:20 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : template +Top-level Entity Name : template +Family : Cyclone IV E +Device : EP4CE10E22C8 +Timing Models : Final +Total logic elements : 16 / 10,320 ( < 1 % ) + Total combinational functions : 15 / 10,320 ( < 1 % ) + Dedicated logic registers : 5 / 10,320 ( < 1 % ) +Total registers : 5 +Total pins : 17 / 92 ( 18 % ) +Total virtual pins : 0 +Total memory bits : 0 / 423,936 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/AHDL_test/output_files/template.flow.rpt b/AHDL_test/output_files/template.flow.rpt new file mode 100644 index 0000000..a123500 --- /dev/null +++ b/AHDL_test/output_files/template.flow.rpt @@ -0,0 +1,124 @@ +Flow report for template +Sat Apr 24 03:42:23 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sat Apr 24 03:42:21 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; template ; +; Top-level Entity Name ; template ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10E22C8 ; +; Timing Models ; Final ; +; Total logic elements ; 16 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 15 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 5 / 10,320 ( < 1 % ) ; +; Total registers ; 5 ; +; Total pins ; 17 / 92 ( 18 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 04/24/2021 03:42:07 ; +; Main task ; Compilation ; +; Revision Name ; template ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 79871138160810.161922492745108 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 408 MB ; 00:00:23 ; +; Fitter ; 00:00:04 ; 1.0 ; 942 MB ; 00:00:04 ; +; Assembler ; 00:00:00 ; 1.0 ; 351 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 444 MB ; 00:00:01 ; +; Total ; 00:00:13 ; -- ; -- ; 00:00:29 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+----------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+----------------+------------+----------------+ +; Analysis & Synthesis ; AW17R3 ; Ubuntu 20.04.2 ; 20 ; x86_64 ; +; Fitter ; AW17R3 ; Ubuntu 20.04.2 ; 20 ; x86_64 ; +; Assembler ; AW17R3 ; Ubuntu 20.04.2 ; 20 ; x86_64 ; +; Timing Analyzer ; AW17R3 ; Ubuntu 20.04.2 ; 20 ; x86_64 ; ++----------------------+------------------+----------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off template -c template +quartus_fit --read_settings_files=off --write_settings_files=off template -c template +quartus_asm --read_settings_files=off --write_settings_files=off template -c template +quartus_sta template -c template + + + diff --git a/AHDL_test/output_files/template.jdi b/AHDL_test/output_files/template.jdi new file mode 100644 index 0000000..074da67 --- /dev/null +++ b/AHDL_test/output_files/template.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/AHDL_test/output_files/template.map.rpt b/AHDL_test/output_files/template.map.rpt new file mode 100644 index 0000000..4e2b85b --- /dev/null +++ b/AHDL_test/output_files/template.map.rpt @@ -0,0 +1,364 @@ +Analysis & Synthesis report for template +Sat Apr 24 03:42:16 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Registers Removed During Synthesis + 9. General Register Statistics + 10. Post-Synthesis Netlist Statistics for Top Partition + 11. Elapsed Time Per Partition + 12. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Apr 24 03:42:16 2021 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; template ; +; Top-level Entity Name ; template ; +; Family ; Cyclone IV E ; +; Total logic elements ; 16 ; +; Total combinational functions ; 15 ; +; Dedicated logic registers ; 5 ; +; Total registers ; 5 ; +; Total pins ; 17 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP4CE10E22C8 ; ; +; Top-level entity name ; template ; template ; +; Family name ; Cyclone IV E ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------+---------+ +; template.bdf ; yes ; User Block Diagram/Schematic File ; /home/zen/a-c4e6e10_exemple/AHDL_test/template.bdf ; ; +; template.tdf ; yes ; User AHDL File ; /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf ; ; +; 7seg_driver.tdf ; yes ; User AHDL File ; /home/zen/a-c4e6e10_exemple/AHDL_test/7seg_driver.tdf ; ; +; test.tdf ; yes ; User AHDL File ; /home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf ; ; +; 7seg_driver.inc ; yes ; Auto-Found AHDL File ; /home/zen/a-c4e6e10_exemple/AHDL_test/7seg_driver.inc ; ; ++----------------------------------+-----------------+------------------------------------+-------------------------------------------------------+---------+ + + ++--------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------------------+ +; Estimated Total logic elements ; 16 ; +; ; ; +; Total combinational functions ; 15 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 3 ; +; -- 3 input functions ; 6 ; +; -- <=2 input functions ; 6 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 15 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 5 ; +; -- Dedicated logic registers ; 5 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 17 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; LED_7seg_driver:inst|switcher[0] ; +; Maximum fan-out ; 10 ; +; Total fan-out ; 78 ; +; Average fan-out ; 1.44 ; ++---------------------------------------------+----------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+-----------------+--------------+ +; |template ; 15 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; |template ; template ; work ; +; |LED_7seg_driver:inst| ; 15 (15) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |template|LED_7seg_driver:inst ; LED_7seg_driver ; work ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++----------------------------------------+-----------------------------------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------+-----------------------------------------------+ +; LED_7seg_driver:inst|in_buf[7][3] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[7][2] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[7][1] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[7][0] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[6][2] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[6][1] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[6][0] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[5][2] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[5][1] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[5][0] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[4][3] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[4][1] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[4][0] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[3][3] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[3][1] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[3][0] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[2][1] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[2][0] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[1][1] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[1][0] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[0][3] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[0][2] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[0][0] ; Stuck at GND due to stuck port data_in ; +; LED_7seg_driver:inst|in_buf[1][2] ; Merged with LED_7seg_driver:inst|in_buf[0][1] ; +; LED_7seg_driver:inst|in_buf[1][3] ; Merged with LED_7seg_driver:inst|in_buf[0][1] ; +; LED_7seg_driver:inst|in_buf[2][2] ; Merged with LED_7seg_driver:inst|in_buf[0][1] ; +; LED_7seg_driver:inst|in_buf[2][3] ; Merged with LED_7seg_driver:inst|in_buf[0][1] ; +; LED_7seg_driver:inst|in_buf[3][2] ; Merged with LED_7seg_driver:inst|in_buf[0][1] ; +; LED_7seg_driver:inst|in_buf[4][2] ; Merged with LED_7seg_driver:inst|in_buf[0][1] ; +; LED_7seg_driver:inst|in_buf[5][3] ; Merged with LED_7seg_driver:inst|in_buf[0][1] ; +; LED_7seg_driver:inst|in_buf[6][3] ; Merged with LED_7seg_driver:inst|in_buf[0][1] ; +; Total Number of Removed Registers = 31 ; ; ++----------------------------------------+-----------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 5 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 17 ; +; cycloneiii_ff ; 5 ; +; plain ; 5 ; +; cycloneiii_lcell_comb ; 16 ; +; normal ; 16 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 1 ; +; 2 data inputs ; 5 ; +; 3 data inputs ; 6 ; +; 4 data inputs ; 3 ; +; ; ; +; Max LUT depth ; 2.00 ; +; Average LUT depth ; 1.43 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 03:42:07 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off template -c template +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Warning (12019): Can't analyze file -- file ../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf is missing +Info (12021): Found 1 design units, including 1 entities, in source file template.bdf + Info (12023): Found entity 1: template +Warning (287002): Group MSB D7 overrides BIT0 = LSB in actual or default Options Statement File: /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf Line: 4 +Warning (287002): Group MSB D3 overrides BIT0 = LSB in actual or default Options Statement File: /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf Line: 4 +Warning (287002): Group MSB dig7 overrides BIT0 = LSB in actual or default Options Statement File: /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf Line: 5 +Warning (287017): Group is used as "D[7..0]" and defined using a different range order ("D[0..7]") File: /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf Line: 20 +Warning (287017): Group is used as "D[3..0]" and defined using a different range order ("D[0..3]") File: /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf Line: 20 +Warning (287013): Variable or input pin "decoder_out" is defined but never used. File: /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf Line: 10 +Info (12021): Found 1 design units, including 1 entities, in source file template.tdf + Info (12023): Found entity 1: LED_7seg_driver File: /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file 7seg_driver.tdf + Info (12023): Found entity 1: 7seg_driver File: /home/zen/a-c4e6e10_exemple/AHDL_test/7seg_driver.tdf Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file test.tdf + Info (12023): Found entity 1: test File: /home/zen/a-c4e6e10_exemple/AHDL_test/test.tdf Line: 1 +Info (12127): Elaborating entity "template" for the top level hierarchy +Info (12128): Elaborating entity "LED_7seg_driver" for hierarchy "LED_7seg_driver:inst" +Info (12128): Elaborating entity "7seg_driver" for hierarchy "LED_7seg_driver:inst|7seg_driver:$00000" File: /home/zen/a-c4e6e10_exemple/AHDL_test/template.tdf Line: 31 +Info (12128): Elaborating entity "test" for hierarchy "test:inst4" +Warning (12001): Port "D[0][4]" does not exist in entity definition of "LED_7seg_driver". The port's range differs between the entity definition and its actual instantiation, "LED_7seg_driver:inst". +Warning (12001): Port "D[1][4]" does not exist in entity definition of "LED_7seg_driver". The port's range differs between the entity definition and its actual instantiation, "LED_7seg_driver:inst". +Warning (12001): Port "D[2][4]" does not exist in entity definition of "LED_7seg_driver". The port's range differs between the entity definition and its actual instantiation, "LED_7seg_driver:inst". +Warning (12001): Port "D[3][4]" does not exist in entity definition of "LED_7seg_driver". The port's range differs between the entity definition and its actual instantiation, "LED_7seg_driver:inst". +Warning (12001): Port "D[4][4]" does not exist in entity definition of "LED_7seg_driver". The port's range differs between the entity definition and its actual instantiation, "LED_7seg_driver:inst". +Warning (12001): Port "D[5][4]" does not exist in entity definition of "LED_7seg_driver". The port's range differs between the entity definition and its actual instantiation, "LED_7seg_driver:inst". +Warning (12001): Port "D[6][4]" does not exist in entity definition of "LED_7seg_driver". The port's range differs between the entity definition and its actual instantiation, "LED_7seg_driver:inst". +Warning (12001): Port "D[7][4]" does not exist in entity definition of "LED_7seg_driver". The port's range differs between the entity definition and its actual instantiation, "LED_7seg_driver:inst". +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "HEX[0]" is stuck at GND + Warning (13410): Pin "HEX[1]" is stuck at GND + Warning (13410): Pin "HEX[2]" is stuck at GND + Warning (13410): Pin "HEX[3]" is stuck at GND + Warning (13410): Pin "HEX[4]" is stuck at GND +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 33 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 2 input pins + Info (21059): Implemented 15 output pins + Info (21061): Implemented 16 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 22 warnings + Info: Peak virtual memory: 415 megabytes + Info: Processing ended: Sat Apr 24 03:42:16 2021 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:23 + + diff --git a/AHDL_test/output_files/template.map.summary b/AHDL_test/output_files/template.map.summary new file mode 100644 index 0000000..f78207d --- /dev/null +++ b/AHDL_test/output_files/template.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Sat Apr 24 03:42:16 2021 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : template +Top-level Entity Name : template +Family : Cyclone IV E +Total logic elements : 16 + Total combinational functions : 15 + Dedicated logic registers : 5 +Total registers : 5 +Total pins : 17 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/AHDL_test/output_files/template.pin b/AHDL_test/output_files/template.pin new file mode 100755 index 0000000..cf4e8f2 --- /dev/null +++ b/AHDL_test/output_files/template.pin @@ -0,0 +1,216 @@ + -- Copyright (C) 2020 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +CHIP "template" ASSIGNED TO AN: EP4CE10E22C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 3 : : : : 1 : +GND : 4 : gnd : : : : +VCCINT : 5 : power : : 1.2V : : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : 7 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : input : 2.5 V : : 1 : N +nSTATUS : 9 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 10 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 : +~ALTERA_DCLK~ : 12 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 13 : input : 2.5 V : : 1 : N +nCONFIG : 14 : : : : 1 : +TDI : 15 : input : : : 1 : +TCK : 16 : input : : : 1 : +VCCIO1 : 17 : power : : 2.5V : 1 : +TMS : 18 : input : : : 1 : +GND : 19 : gnd : : : : +TDO : 20 : output : : : 1 : +nCE : 21 : : : : 1 : +GND : 22 : gnd : : : : +GND+ : 23 : : : : 1 : +GND+ : 24 : : : : 2 : +GND+ : 25 : : : : 2 : +VCCIO2 : 26 : power : : 2.5V : 2 : +GND : 27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 28 : : : : 2 : +VCCINT : 29 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 30 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 31 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 32 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 33 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 34 : : : : 2 : +VCCA1 : 35 : power : : 2.5V : : +GNDA1 : 36 : gnd : : : : +VCCD_PLL1 : 37 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 38 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 : +VCCIO3 : 40 : power : : 2.5V : 3 : +GND : 41 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 : +VCCINT : 45 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 3 : +VCCIO3 : 47 : power : : 2.5V : 3 : +GND : 48 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 52 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 53 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 54 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 55 : : : : 4 : +VCCIO4 : 56 : power : : 2.5V : 4 : +GND : 57 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 : +VCCINT : 61 : power : : 1.2V : : +VCCIO4 : 62 : power : : 2.5V : 4 : +GND : 63 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 65 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 66 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 70 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 73 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 74 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 75 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 77 : : : : 5 : +VCCINT : 78 : power : : 1.2V : : +GND : 79 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 80 : : : : 5 : +VCCIO5 : 81 : power : : 2.5V : 5 : +GND : 82 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 84 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 85 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 86 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 5 : +GND+ : 88 : : : : 5 : +GND+ : 89 : : : : 5 : +K[2] : 90 : input : 2.5 V : : 6 : Y +K[3] : 91 : input : 2.5 V : : 6 : Y +CONF_DONE : 92 : : : : 6 : +VCCIO6 : 93 : power : : 2.5V : 6 : +MSEL0 : 94 : : : : 6 : +GND : 95 : gnd : : : : +MSEL1 : 96 : : : : 6 : +MSEL2 : 97 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 101 : output : 2.5 V : : 6 : N +VCCINT : 102 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 105 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 106 : : : : 6 : +VCCA2 : 107 : power : : 2.5V : : +GNDA2 : 108 : gnd : : : : +VCCD_PLL2 : 109 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 110 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 111 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 112 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 113 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 114 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 115 : : : : 7 : +VCCINT : 116 : power : : 1.2V : : +VCCIO7 : 117 : power : : 2.5V : 7 : +GND : 118 : gnd : : : : +SEG[6] : 119 : output : 2.5 V : : 7 : Y +SEG[5] : 120 : output : 2.5 V : : 7 : Y +SEG[4] : 121 : output : 2.5 V : : 7 : Y +VCCIO7 : 122 : power : : 2.5V : 7 : +GND : 123 : gnd : : : : +SEG[3] : 124 : output : 2.5 V : : 7 : Y +SEG[2] : 125 : output : 2.5 V : : 7 : Y +SEG[1] : 126 : output : 2.5 V : : 7 : Y +SEG[0] : 127 : output : 2.5 V : : 7 : Y +HEX[0] : 128 : output : 2.5 V : : 8 : Y +HEX[1] : 129 : output : 2.5 V : : 8 : Y +VCCIO8 : 130 : power : : 2.5V : 8 : +GND : 131 : gnd : : : : +HEX[2] : 132 : output : 2.5 V : : 8 : Y +HEX[3] : 133 : output : 2.5 V : : 8 : Y +VCCINT : 134 : power : : 1.2V : : +HEX[4] : 135 : output : 2.5 V : : 8 : Y +HEX[5] : 136 : output : 2.5 V : : 8 : Y +HEX[6] : 137 : output : 2.5 V : : 8 : Y +HEX[7] : 138 : output : 2.5 V : : 8 : Y +VCCIO8 : 139 : power : : 2.5V : 8 : +GND : 140 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 141 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 142 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 143 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 144 : : : : 8 : +GND : EPAD : : : : : diff --git a/AHDL_test/output_files/template.sld b/AHDL_test/output_files/template.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/AHDL_test/output_files/template.sld @@ -0,0 +1 @@ + diff --git a/AHDL_test/output_files/template.sof b/AHDL_test/output_files/template.sof new file mode 100644 index 0000000..90f3110 Binary files /dev/null and b/AHDL_test/output_files/template.sof differ diff --git a/AHDL_test/output_files/template.sta.rpt b/AHDL_test/output_files/template.sta.rpt new file mode 100644 index 0000000..c53da19 --- /dev/null +++ b/AHDL_test/output_files/template.sta.rpt @@ -0,0 +1,707 @@ +Timing Analyzer report for template +Sat Apr 24 03:42:23 2021 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Slow 1200mV 85C Model Setup: 'K[2]' + 13. Slow 1200mV 85C Model Hold: 'K[2]' + 14. Slow 1200mV 85C Model Metastability Summary + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Slow 1200mV 0C Model Setup: 'K[2]' + 22. Slow 1200mV 0C Model Hold: 'K[2]' + 23. Slow 1200mV 0C Model Metastability Summary + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Fast 1200mV 0C Model Setup: 'K[2]' + 30. Fast 1200mV 0C Model Hold: 'K[2]' + 31. Fast 1200mV 0C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1200mv 0c Model) + 36. Signal Integrity Metrics (Slow 1200mv 85c Model) + 37. Signal Integrity Metrics (Fast 1200mv 0c Model) + 38. Setup Transfers + 39. Hold Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths Summary + 43. Clock Status Summary + 44. Unconstrained Input Ports + 45. Unconstrained Output Ports + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; template ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE10E22C8 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.3% ; +; Processors 3-4 ; 0.2% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +; K[2] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { K[2] } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; 737.46 MHz ; 250.0 MHz ; K[2] ; limit due to minimum period restriction (max I/O toggle rate) ; ++------------+-----------------+------------+---------------------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++-------+--------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+--------------------+ +; K[2] ; -0.356 ; -0.706 ; ++-------+--------+--------------------+ + + ++------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++-------+-------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+--------------------+ +; K[2] ; 0.453 ; 0.000 ; ++-------+-------+--------------------+ + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++-------+--------+----------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+----------------------------------+ +; K[2] ; -3.000 ; -10.435 ; ++-------+--------+----------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'K[2]' ; ++--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; -0.356 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.276 ; +; -0.325 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.245 ; +; -0.324 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.244 ; +; -0.026 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.946 ; +; -0.026 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.946 ; +; -0.023 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.943 ; +; 0.062 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ; +; 0.062 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ; +; 0.062 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ; +; 0.098 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.822 ; ++--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'K[2]' ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.453 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ; +; 0.453 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ; +; 0.453 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ; +; 0.465 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.758 ; +; 0.524 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.817 ; +; 0.527 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.820 ; +; 0.527 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.820 ; +; 0.772 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.065 ; +; 0.821 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.114 ; +; 0.840 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.133 ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++-----------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; 820.34 MHz ; 250.0 MHz ; K[2] ; limit due to minimum period restriction (max I/O toggle rate) ; ++------------+-----------------+------------+---------------------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++-------+--------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-------------------+ +; K[2] ; -0.219 ; -0.412 ; ++-------+--------+-------------------+ + + ++-----------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++-------+-------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-------------------+ +; K[2] ; 0.401 ; 0.000 ; ++-------+-------+-------------------+ + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++-------+--------+---------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------------------------+ +; K[2] ; -3.000 ; -10.435 ; ++-------+--------+---------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'K[2]' ; ++--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; -0.219 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.148 ; +; -0.194 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.123 ; +; -0.193 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.122 ; +; 0.070 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.859 ; +; 0.070 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.859 ; +; 0.073 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.856 ; +; 0.159 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ; +; 0.159 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ; +; 0.159 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ; +; 0.184 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.745 ; ++--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'K[2]' ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.401 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ; +; 0.401 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ; +; 0.401 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ; +; 0.416 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.684 ; +; 0.482 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.750 ; +; 0.484 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.752 ; +; 0.484 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.752 ; +; 0.716 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.984 ; +; 0.762 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 1.030 ; +; 0.782 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 1.050 ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++-------+-------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+--------------------+ +; K[2] ; 0.404 ; 0.000 ; ++-------+-------+--------------------+ + + ++-----------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++-------+-------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-------------------+ +; K[2] ; 0.187 ; 0.000 ; ++-------+-------+-------------------+ + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++-------+--------+---------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------------------------+ +; K[2] ; -3.000 ; -8.315 ; ++-------+--------+---------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'K[2]' ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.404 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.547 ; +; 0.420 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.531 ; +; 0.422 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.529 ; +; 0.552 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.399 ; +; 0.553 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.398 ; +; 0.560 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.391 ; +; 0.592 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ; +; 0.592 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ; +; 0.592 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ; +; 0.601 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.350 ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'K[2]' ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.187 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ; +; 0.187 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ; +; 0.194 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.314 ; +; 0.214 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.334 ; +; 0.215 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.335 ; +; 0.216 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.336 ; +; 0.310 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.430 ; +; 0.337 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.457 ; +; 0.348 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.468 ; ++-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+--------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+--------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -0.356 ; 0.187 ; N/A ; N/A ; -3.000 ; +; K[2] ; -0.356 ; 0.187 ; N/A ; N/A ; -3.000 ; +; Design-wide TNS ; -0.706 ; 0.0 ; 0.0 ; 0.0 ; -10.435 ; +; K[2] ; -0.706 ; 0.000 ; N/A ; N/A ; -10.435 ; ++------------------+--------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; HEX[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; SEG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; SEG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; SEG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; SEG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; SEG[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; SEG[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; SEG[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; K[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; K[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; +; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; +; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; K[2] ; K[2] ; 10 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; K[2] ; K[2] ; 10 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 1 ; 1 ; +; Unconstrained Input Port Paths ; 1 ; 1 ; +; Unconstrained Output Ports ; 10 ; 10 ; +; Unconstrained Output Port Paths ; 41 ; 41 ; ++---------------------------------+-------+------+ + + ++-------------------------------------+ +; Clock Status Summary ; ++--------+-------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++--------+-------+------+-------------+ +; K[2] ; K[2] ; Base ; Constrained ; ++--------+-------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; K[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; K[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; HEX[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; HEX[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SEG[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Sat Apr 24 03:42:22 2021 +Info: Command: quartus_sta template -c template +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name K[2] K[2] +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -0.356 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -0.356 -0.706 K[2] +Info (332146): Worst-case hold slack is 0.453 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.453 0.000 K[2] +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.000 -10.435 K[2] +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -0.219 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -0.219 -0.412 K[2] +Info (332146): Worst-case hold slack is 0.401 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.401 0.000 K[2] +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.000 -10.435 K[2] +Info: Analyzing Fast 1200mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332146): Worst-case setup slack is 0.404 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.404 0.000 K[2] +Info (332146): Worst-case hold slack is 0.187 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.187 0.000 K[2] +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.000 -8.315 K[2] +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 444 megabytes + Info: Processing ended: Sat Apr 24 03:42:23 2021 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/AHDL_test/output_files/template.sta.summary b/AHDL_test/output_files/template.sta.summary new file mode 100644 index 0000000..90fd41a --- /dev/null +++ b/AHDL_test/output_files/template.sta.summary @@ -0,0 +1,41 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'K[2]' +Slack : -0.356 +TNS : -0.706 + +Type : Slow 1200mV 85C Model Hold 'K[2]' +Slack : 0.453 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'K[2]' +Slack : -3.000 +TNS : -10.435 + +Type : Slow 1200mV 0C Model Setup 'K[2]' +Slack : -0.219 +TNS : -0.412 + +Type : Slow 1200mV 0C Model Hold 'K[2]' +Slack : 0.401 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'K[2]' +Slack : -3.000 +TNS : -10.435 + +Type : Fast 1200mV 0C Model Setup 'K[2]' +Slack : 0.404 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'K[2]' +Slack : 0.187 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'K[2]' +Slack : -3.000 +TNS : -8.315 + +------------------------------------------------------------ diff --git a/AHDL_test/template.bdf b/AHDL_test/template.bdf new file mode 100644 index 0000000..37da4a6 --- /dev/null +++ b/AHDL_test/template.bdf @@ -0,0 +1,163 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 136 296 304 312) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "K[2]" (rect 5 0 25 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 80 312 136 328)) +) +(pin + (input) + (rect -104 224 64 240) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "K[3]" (rect 5 0 28 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect -8 264 48 280)) +) +(pin + (output) + (rect 496 280 672 296) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HEX[0..7]" (rect 90 0 138 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 616 248 672 264)) +) +(pin + (output) + (rect 496 296 672 312) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "SEG[0..6]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 672 312 736 328)) +) +(symbol + (rect 304 256 496 336) + (text "LED_7seg_driver" (rect 5 0 92 11)(font "Arial" )) + (text "inst" (rect 8 64 26 75)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "D[0..7][0..4]" (rect 0 0 57 11)(font "Arial" )) + (text "D[0..7][0..4]" (rect 21 27 78 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clk" (rect 0 0 15 11)(font "Arial" )) + (text "clk" (rect 21 43 36 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 192 32) + (output) + (text "dig[0..7]" (rect 0 0 40 11)(font "Arial" )) + (text "dig[0..7]" (rect 138 27 171 38)(font "Arial" )) + (line (pt 192 32)(pt 176 32)(line_width 3)) + ) + (port + (pt 192 48) + (output) + (text "SEG[6..0]" (rect 0 0 48 11)(font "Arial" )) + (text "SEG[6..0]" (rect 131 43 171 54)(font "Arial" )) + (line (pt 192 48)(pt 176 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 176 64)) + ) +) +(symbol + (rect 64 200 248 280) + (text "test" (rect 5 0 23 11)(font "Arial" )) + (text "inst4" (rect 8 64 33 77)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "test" (rect 0 0 18 11)(font "Arial" )) + (text "test" (rect 21 27 39 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 184 32) + (output) + (text "number[7..0][4..0]" (rect 0 0 86 11)(font "Arial" )) + (text "number[7..0][4..0]" (rect 91 27 177 38)(font "Arial" )) + (line (pt 184 32)(pt 168 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 168 64)) + ) +) +(connector + (pt 304 288) + (pt 280 288) + (bus) +) +(connector + (pt 280 288) + (pt 280 232) + (bus) +) +(connector + (pt 248 232) + (pt 280 232) + (bus) +) diff --git a/AHDL_test/template.bsf b/AHDL_test/template.bsf new file mode 100644 index 0000000..fb0306a --- /dev/null +++ b/AHDL_test/template.bsf @@ -0,0 +1,44 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 112 112) + (text "template" (rect 5 0 58 15)(font "Intel Clear" (font_size 8))) + (text "inst" (rect 8 79 28 92)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "K[2]" (rect 0 0 24 15)(font "Intel Clear" (font_size 8))) + (text "K[2]" (rect 21 27 45 42)(font "Intel Clear" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 96 32) + (output) + (text "D[5]" (rect 0 0 24 15)(font "Intel Clear" (font_size 8))) + (text "D[5]" (rect 51 27 75 42)(font "Intel Clear" (font_size 8))) + (line (pt 96 32)(pt 80 32)) + ) + (drawing + (rectangle (rect 16 16 80 80)) + ) +) diff --git a/AHDL_test/template.qpf b/AHDL_test/template.qpf new file mode 100755 index 0000000..455ea33 --- /dev/null +++ b/AHDL_test/template.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 20:32:51 October 18, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "20:32:51 October 18, 2020" + +# Revisions + +PROJECT_REVISION = "template" diff --git a/AHDL_test/template.qsf b/AHDL_test/template.qsf new file mode 100755 index 0000000..38b8234 --- /dev/null +++ b/AHDL_test/template.qsf @@ -0,0 +1,123 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 20:32:51 October 18, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# template_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE10E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY template +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:51 OCTOBER 18, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_128 -to HEX[0] +set_location_assignment PIN_129 -to HEX[1] +set_location_assignment PIN_132 -to HEX[2] +set_location_assignment PIN_133 -to HEX[3] +set_location_assignment PIN_135 -to HEX[4] +set_location_assignment PIN_136 -to HEX[5] +set_location_assignment PIN_137 -to HEX[6] +set_location_assignment PIN_138 -to HEX[7] +set_location_assignment PIN_72 -to D[3] +set_location_assignment PIN_73 -to D[4] +set_location_assignment PIN_74 -to D[5] +set_location_assignment PIN_80 -to D[6] +set_location_assignment PIN_83 -to D[7] +set_location_assignment PIN_84 -to D[8] +set_location_assignment PIN_77 -to D[9] +set_location_assignment PIN_76 -to D[10] +set_location_assignment PIN_75 -to D[11] +set_location_assignment PIN_71 -to D[12] +set_location_assignment PIN_70 -to D[13] +set_location_assignment PIN_69 -to D[14] +set_location_assignment PIN_58 -to SW[1] +set_location_assignment PIN_60 -to SW[3] +set_location_assignment PIN_64 -to SW[4] +set_location_assignment PIN_65 -to SW[5] +set_location_assignment PIN_66 -to SW[6] +set_location_assignment PIN_67 -to SW[7] +set_location_assignment PIN_59 -to SW[2] +set_location_assignment PIN_68 -to SW[8] +set_location_assignment PIN_90 -to K[2] +set_location_assignment PIN_91 -to K[3] +set_location_assignment PIN_87 -to K[4] +set_location_assignment PIN_86 -to K[5] +set_location_assignment PIN_141 -to BELL +set_location_assignment PIN_2 -to VGA_R +set_location_assignment PIN_1 -to VGA_G +set_location_assignment PIN_144 -to VGA_B +set_location_assignment PIN_143 -to VGA_VS +set_location_assignment PIN_142 -to VGA_HS +set_location_assignment PIN_3 -to MEM_SDA +set_location_assignment PIN_7 -to MEM_SCK +set_location_assignment PIN_10 -to PS_2_DATA +set_location_assignment PIN_11 -to PS_2_SCK +set_location_assignment PIN_23 -to CLK_50M +set_location_assignment PIN_24 -to CLK_USER +set_location_assignment PIN_114 -to UART_TX +set_location_assignment PIN_113 -to UART_RX +set_location_assignment PIN_101 -to LCD_D[0] +set_location_assignment PIN_103 -to LCD_D[1] +set_location_assignment PIN_104 -to LCD_D[2] +set_location_assignment PIN_105 -to LCD_D[3] +set_location_assignment PIN_106 -to LCD_D[4] +set_location_assignment PIN_110 -to LCD_D[5] +set_location_assignment PIN_111 -to LCD_D[6] +set_location_assignment PIN_112 -to LCD_D[7] +set_location_assignment PIN_85 -to LCD_RS +set_location_assignment PIN_99 -to LCD_WR +set_location_assignment PIN_100 -to LCD_EN +set_global_assignment -name BDF_FILE "../../../Рабочий стол/a-c4e6e10_exemple/AHDL_test/template.bdf" +set_global_assignment -name BDF_FILE template.bdf +set_global_assignment -name AHDL_FILE template.tdf +set_global_assignment -name AHDL_FILE 7seg_driver.tdf +set_location_assignment PIN_127 -to SEG[0] +set_location_assignment PIN_126 -to SEG[1] +set_location_assignment PIN_125 -to SEG[2] +set_location_assignment PIN_124 -to SEG[3] +set_location_assignment PIN_121 -to SEG[4] +set_location_assignment PIN_120 -to SEG[5] +set_location_assignment PIN_119 -to SEG[6] +set_location_assignment PIN_115 -to SEG[7] +set_global_assignment -name AHDL_FILE test.tdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/AHDL_test/template.qws b/AHDL_test/template.qws new file mode 100644 index 0000000..43cfdac Binary files /dev/null and b/AHDL_test/template.qws differ diff --git a/AHDL_test/template.tdf b/AHDL_test/template.tdf new file mode 100644 index 0000000..d670aa3 --- /dev/null +++ b/AHDL_test/template.tdf @@ -0,0 +1,40 @@ +include "7seg_driver"; + +subdesign LED_7seg_driver ( + D[0..7][0..3], clk : input; + dig[0..7], seg[6..0] : output; +) + +variable + in_buf[7..0][3..0] : DFF; + decoder_out[7..0][7..0] : NODE; + switcher[3..0] : DFF; + +begin + +DEFAULTS + switcher[].d = 0; +END DEFAULTS; + + in_buf[][].clk = clk; + in_buf[7..0][3..0].d = D[7..0][3..0]; + + switcher[].clk = clk; + if switcher[].q == 7 + THEN + switcher[].d = 0; + ELSE + switcher[].d = switcher[].q + 1; + END IF; + + CASE switcher[].q IS + WHEN 0 => dig[] = 0; seg[] = 7seg_driver(in_buf[0][].q); + WHEN 1 => dig[] = 1; seg[] = 7seg_driver(in_buf[1][].q); + WHEN 2 => dig[] = 2; seg[] = 7seg_driver(in_buf[2][].q); + WHEN 3 => dig[] = 3; seg[] = 7seg_driver(in_buf[3][].q); + WHEN 4 => dig[] = 4; seg[] = 7seg_driver(in_buf[4][].q); + WHEN 5 => dig[] = 5; seg[] = 7seg_driver(in_buf[5][].q); + WHEN 6 => dig[] = 6; seg[] = 7seg_driver(in_buf[6][].q); + WHEN 7 => dig[] = 7; seg[] = 7seg_driver(in_buf[7][].q); + END CASE; +end; \ No newline at end of file diff --git a/AHDL_test/template.tdf.bak b/AHDL_test/template.tdf.bak new file mode 100644 index 0000000..c2299f8 --- /dev/null +++ b/AHDL_test/template.tdf.bak @@ -0,0 +1,24 @@ +subdesign LED_7seg_driver { + D[8..0][4..0], CLK : input; + SEG[8..0], NUM[7..0] : output; +} + +variable + in_buf[8..0][4..0] : DFF; + decoder_out[8..0][7..0] : NODE; + +begin + in_buf[].clk = CLK; + in_buf[8..0][4..0] = D[8..0][4..0]; + + FOR i=1 TO 8 GENERATE + decoder_out[i] = + + + in_buf[i][0] + END GENERATE; + + + + +end; \ No newline at end of file diff --git a/AHDL_test/template_assignment_defaults.qdf b/AHDL_test/template_assignment_defaults.qdf new file mode 100755 index 0000000..67d454d --- /dev/null +++ b/AHDL_test/template_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 17:03:14 April 10, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/AHDL_test/test.bsf b/AHDL_test/test.bsf new file mode 100644 index 0000000..3ae5acd --- /dev/null +++ b/AHDL_test/test.bsf @@ -0,0 +1,44 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 200 96) + (text "test" (rect 5 0 19 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "test" (rect 0 0 14 12)(font "Arial" )) + (text "test" (rect 21 27 35 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 184 32) + (output) + (text "number[7..0][4..0]" (rect 0 0 71 12)(font "Arial" )) + (text "number[7..0][4..0]" (rect 92 27 163 39)(font "Arial" )) + (line (pt 184 32)(pt 168 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 168 64)(line_width 1)) + ) +) diff --git a/AHDL_test/test.tdf b/AHDL_test/test.tdf new file mode 100644 index 0000000..529d43a --- /dev/null +++ b/AHDL_test/test.tdf @@ -0,0 +1,27 @@ +SUBDESIGN test( + test : INPUT; + number[7..0][4..0] : OUTPUT;) + +BEGIN + IF test == 1 + THEN + number[0][] = 1; + number[1][] = 2; + number[2][] = 3; + number[3][] = 4; + number[4][] = 5; + number[5][] = 6; + number[6][] = 7; + number[7][] = 8; + ELSE + number[0][] = 0; + number[1][] = 0; + number[2][] = 0; + number[3][] = 0; + number[4][] = 0; + number[5][] = 0; + number[6][] = 0; + number[7][] = 0; + + END IF; +END; \ No newline at end of file diff --git a/AHDL_test/test.tdf.bak b/AHDL_test/test.tdf.bak new file mode 100644 index 0000000..3c9cd83 --- /dev/null +++ b/AHDL_test/test.tdf.bak @@ -0,0 +1,28 @@ +SUDESIGN decode1 + ( + test : INPUT; + number[8..0][4..0] : OUTPUT; + ) +BEGIN + IF test == 1 + THEN + number[0] = 1; + number[1] = 2; + number[2] = 3; + number[3] = 4; + number[4] = 5; + number[5] = 6; + number[6] = 7; + number[7] = 8; + ELSE + number[0] = 0; + number[1] = 0; + number[2] = 0; + number[3] = 0; + number[4] = 0; + number[5] = 0; + number[6] = 0; + number[7] = 0; + + END IF; +END; \ No newline at end of file diff --git a/README.md b/README.md index cbb90c6..1626eb9 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ Примеры кода для A-C4E6E10. -Далее крадко расскажу о том что делать если вы в линухе: +Далее кратко расскажу о том что делать если вы в линухе: ## Установка Quartus @@ -18,6 +18,49 @@ tar -xvf Quartus-lite-20.1.1.720-linux.tar rm -r setup.sh readme.txt components/ Quartus-lite-20.1.1.720-linux.tar ``` +Для того чтобы иметь возможность запускать квартус из консоли, необходимо в ```~/.bashrc``` добавить следующие строки: + +```bash +alias quartus='nohup $QSYS_ROOTDIR/quartus > /dev/null &' +#nohup нужен для того чтобы приложение продолжило работу после закрытия терминала +``` + +Также у меня возникла следующая проблема (эта ошибка высветится в терминале если запускать через него без alias): + +```txt +Gtk-Message: 12:28:39.404: Failed to load module "canberra-gtk-module" +``` + +Решается очень просто: + +```bash +sudo apt install libcanberra-gtk-module +``` + +> Обратите внимание что не стоит бездумно копировать команды отсюда т.к. они для МОЕГО пользователя и МОЕЙ версии quartus. + +Также у меня не заработала прошивка через usb blaster. Она связанно с тем что мы ставили программу не от рута, а значит скрипт установки не смог прописать udev rules, а значит это нужно сделать в ручную. + +Для этого в UBUNTU создаем файл ```/etc/udev/rules.d/51-usbblaster.rules``` и заполняем его: + +```txt +# USB Blaster +SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6001", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c" +SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6002", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c" +SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6003", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c" + +# USB Blaster II +SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6010", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c" +SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6810", MODE="0666", NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}", RUN+="/bin/chmod 0666 %c" +``` + +После чего отключаем и снова подключаем blaster к usb. Подробнее [тут](https://rocketboards.org/foswiki/view/Documentation/UsingUSBBlasterUnderLinux). + 3) Тут ставим икарус и gtk-wave но это в другой раз. ## Работа с Quartus + +В данном репозитории вы найдете ```tamplate``` который нужно использовать как заготовку проекта, по своей сути это просто пустой проект в котором уже расставлены все пины в соответствии с платой. + +Так-же в этом репозитории есть папка ```docs``` в которой будет лежать схема отладочной платы и распиновка. + diff --git a/docs/A-C4E6 PIN.xls b/docs/A-C4E6 PIN.xls new file mode 100644 index 0000000..394066d Binary files /dev/null and b/docs/A-C4E6 PIN.xls differ diff --git a/docs/A-C4E6-SCH.pdf b/docs/A-C4E6-SCH.pdf new file mode 100644 index 0000000..9ec262e Binary files /dev/null and b/docs/A-C4E6-SCH.pdf differ diff --git a/template/db/.cmp.kpt b/template/db/.cmp.kpt new file mode 100755 index 0000000..558ee92 Binary files /dev/null and b/template/db/.cmp.kpt differ diff --git a/template/db/prev_cmp_template.qmsg b/template/db/prev_cmp_template.qmsg new file mode 100755 index 0000000..e9c6e34 --- /dev/null +++ b/template/db/prev_cmp_template.qmsg @@ -0,0 +1,19 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1603042773582 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603042773587 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 18 20:39:33 2020 " "Processing started: Sun Oct 18 20:39:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1603042773587 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1603042773587 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off template -c template --plan " "Command: quartus_fit --read_settings_files=on --write_settings_files=off template -c template --plan" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1603042773587 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1603042773664 ""} +{ "Info" "0" "" "Project = template" { } { } 0 0 "Project = template" 0 0 "Fitter" 0 0 1603042773664 ""} +{ "Info" "0" "" "Revision = template" { } { } 0 0 "Revision = template" 0 0 "Fitter" 0 0 1603042773664 ""} +{ "Warning" "WQFIT_LEGACY_FLOW_QSYN_NOT_RUN_CHECK_IOS_WARNING" "template I/O Assignment Analysis " "Analysis and Synthesis (quartus_map) with top-level entity name \"template\" was not run before running I/O Assignment Analysis -- I/O Assignment Analysis will check only I/O assignments on the reserved pins" { } { } 0 11747 "Analysis and Synthesis (quartus_map) with top-level entity name \"%1!s!\" was not run before running %2!s! -- %2!s! will check only I/O assignments on the reserved pins" 0 0 "Fitter" 0 -1 1603042773710 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1603042773835 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1603042773835 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "template EP4CE10E22C8 " "Selected device EP4CE10E22C8 for design \"template\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1603042773838 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1603042773892 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1603042773892 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1603042773995 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6E22C8 " "Device EP4CE6E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1603042774008 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1603042774008 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1603042774008 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1603042774008 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/Users/ZEN/Desktop/A_C4E6E10/template/" { { 0 { 0 ""} 0 6 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1603042774009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/ZEN/Desktop/A_C4E6E10/template/" { { 0 { 0 ""} 0 8 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1603042774009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/ZEN/Desktop/A_C4E6E10/template/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1603042774009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/Users/ZEN/Desktop/A_C4E6E10/template/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1603042774009 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/ZEN/Desktop/A_C4E6E10/template/" { { 0 { 0 ""} 0 14 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1603042774009 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1603042774009 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX_A " "Node \"HEX_A\" is assigned to location or region, but does not exist in design" { } { { "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/18.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX_A" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1603042774430 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1603042774430 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1603042774430 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1603042774435 ""} +{ "Info" "IQEXE_ERROR_COUNT" "I/O Assignment Analysis 0 s 6 s Quartus Prime " "Quartus Prime I/O Assignment Analysis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4935 " "Peak virtual memory: 4935 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1603042774478 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 18 20:39:34 2020 " "Processing ended: Sun Oct 18 20:39:34 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1603042774478 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1603042774478 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1603042774478 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1603042774478 ""} diff --git a/template/db/template.db_info b/template/db/template.db_info new file mode 100755 index 0000000..460e57b --- /dev/null +++ b/template/db/template.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Sat Apr 10 17:03:14 2021 diff --git a/template/db/template.sld_design_entry.sci b/template/db/template.sld_design_entry.sci new file mode 100755 index 0000000..586cc7a Binary files /dev/null and b/template/db/template.sld_design_entry.sci differ diff --git a/template/output_files/template.done b/template/output_files/template.done new file mode 100755 index 0000000..92e884f --- /dev/null +++ b/template/output_files/template.done @@ -0,0 +1 @@ +Sun Oct 18 20:45:59 2020 diff --git a/template/output_files/template.fit.rpt b/template/output_files/template.fit.rpt new file mode 100755 index 0000000..1355e1f --- /dev/null +++ b/template/output_files/template.fit.rpt @@ -0,0 +1,319 @@ +I/O Assignment Analysis report for template +Sun Oct 18 20:45:58 2020 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. I/O Assignment Analysis Summary + 3. Parallel Compilation + 4. Fitter Messages + 5. Ignored Assignments + 6. Pin-Out File + 7. All Package Pins + 8. I/O Bank Usage + 9. I/O Assignment Analysis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++------------------------------------------------------------------------------+ +; I/O Assignment Analysis Summary ; ++--------------------------------+---------------------------------------------+ +; I/O Assignment Analysis Status ; Successful - Sun Oct 18 20:45:58 2020 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ; +; Revision Name ; template ; +; Top-level Entity Name ; template ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10E22C8 ; +; Timing Models ; Final ; +; Total pins ; 0 / 92 ( 0 % ) ; +; Total virtual pins ; 0 ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++--------------------------------+---------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (11747): Analysis and Synthesis (quartus_map) with top-level entity name "template" was not run before running I/O Assignment Analysis -- I/O Assignment Analysis will check only I/O assignments on the reserved pins +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EP4CE10E22C8 for design "template" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE6E22C8 is compatible + Info (176445): Device EP4CE15E22C8 is compatible + Info (176445): Device EP4CE22E22C8 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101 +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "HEX_A" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info: Quartus Prime I/O Assignment Analysis was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 4938 megabytes + Info: Processing ended: Sun Oct 18 20:45:58 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + ++----------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; HEX_A ; PIN_127 ; QSF Assignment ; ++----------+----------------+--------------+------------+---------------+----------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/ZEN/Desktop/A_C4E6E10/template/output_files/template.pin. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 3 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 6 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 7 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 8 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 9 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; 10 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 11 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 12 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 13 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 14 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; 15 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 16 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 17 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 18 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 20 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 21 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; 22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 23 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 24 ; 25 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 25 ; 26 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 26 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 28 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 29 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 30 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 31 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 32 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 33 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 34 ; 41 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 35 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 36 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 37 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 38 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 39 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 40 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 41 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 42 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 43 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 44 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 45 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 46 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 47 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 48 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 49 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 50 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 51 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 52 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 53 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 54 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 55 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 56 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 57 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 58 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 59 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 60 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 61 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 62 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 63 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 64 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 65 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 66 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 67 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 68 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 69 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 70 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 71 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 72 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 73 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 74 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 75 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 76 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 77 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 78 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 81 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 82 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 83 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 84 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 85 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 86 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 87 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 88 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 89 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 90 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 91 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 92 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; 93 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 94 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; 95 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 96 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; 97 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; 97 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; 98 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 99 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 100 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 101 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 102 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 103 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 104 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 105 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 106 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 107 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 108 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 109 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 110 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 111 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 112 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 113 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 114 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 115 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 116 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 117 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 118 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 119 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 120 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 121 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 122 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 123 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 124 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 125 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 126 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 127 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 128 ; 177 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 129 ; 178 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 130 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 131 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 132 ; 181 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 133 ; 182 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 134 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 135 ; 185 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 136 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 137 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 138 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 139 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 141 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 142 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 143 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 144 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; EPAD ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1 ; 4 / 11 ( 36 % ) ; 2.5V ; -- ; +; 2 ; 0 / 8 ( 0 % ) ; 2.5V ; -- ; +; 3 ; 0 / 11 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 1 / 10 ( 10 % ) ; 2.5V ; -- ; +; 7 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++----------------------------------+ +; I/O Assignment Analysis Messages ; ++----------------------------------+ +Warning (11747): Analysis and Synthesis (quartus_map) with top-level entity name "template" was not run before running I/O Assignment Analysis -- I/O Assignment Analysis will check only I/O assignments on the reserved pins +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EP4CE10E22C8 for design "template" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE6E22C8 is compatible + Info (176445): Device EP4CE15E22C8 is compatible + Info (176445): Device EP4CE22E22C8 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101 +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "HEX_A" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info: Quartus Prime I/O Assignment Analysis was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 4938 megabytes + Info: Processing ended: Sun Oct 18 20:45:58 2020 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/template/output_files/template.fit.summary b/template/output_files/template.fit.summary new file mode 100755 index 0000000..3af61c8 --- /dev/null +++ b/template/output_files/template.fit.summary @@ -0,0 +1,10 @@ +I/O Assignment Analysis Status : Successful - Sun Oct 18 20:45:58 2020 +Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Lite Edition +Revision Name : template +Top-level Entity Name : template +Family : Cyclone IV E +Device : EP4CE10E22C8 +Timing Models : Final +Total pins : 0 / 92 ( 0 % ) +Total virtual pins : 0 +Total PLLs : 0 / 2 ( 0 % ) diff --git a/template/output_files/template.flow.rpt b/template/output_files/template.flow.rpt new file mode 100755 index 0000000..808045b --- /dev/null +++ b/template/output_files/template.flow.rpt @@ -0,0 +1,68 @@ +Flow report for template +Sun Oct 18 20:45:58 2020 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Messages + 5. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Sun Oct 18 20:45:58 2020 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ; +; Revision Name ; template ; +; Top-level Entity Name ; template ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10E22C8 ; +; Timing Models ; Final ; +; Total logic elements ; 1 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 1 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 10,320 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 0 / 92 ( 0 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 10/18/2020 20:45:58 ; +; Main task ; Compilation ; +; Revision Name ; template ; ++-------------------+---------------------+ + + diff --git a/template/output_files/template.pin b/template/output_files/template.pin new file mode 100755 index 0000000..e9e2164 --- /dev/null +++ b/template/output_files/template.pin @@ -0,0 +1,215 @@ + -- Copyright (C) 2018 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +CHIP "template" ASSIGNED TO AN: EP4CE10E22C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 3 : : : : 1 : +GND : 4 : gnd : : : : +VCCINT : 5 : power : : 1.2V : : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : 7 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : input : 2.5 V : : 1 : N +nSTATUS : 9 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 10 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 : +~ALTERA_DCLK~ : 12 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 13 : input : 2.5 V : : 1 : N +nCONFIG : 14 : : : : 1 : +TDI : 15 : input : : : 1 : +TCK : 16 : input : : : 1 : +VCCIO1 : 17 : power : : 2.5V : 1 : +TMS : 18 : input : : : 1 : +GND : 19 : gnd : : : : +TDO : 20 : output : : : 1 : +nCE : 21 : : : : 1 : +GND : 22 : gnd : : : : +GND+ : 23 : : : : 1 : +GND+ : 24 : : : : 2 : +GND+ : 25 : : : : 2 : +VCCIO2 : 26 : power : : 2.5V : 2 : +GND : 27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 28 : : : : 2 : +VCCINT : 29 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 30 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 31 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 32 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 33 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 34 : : : : 2 : +VCCA1 : 35 : power : : 2.5V : : +GNDA1 : 36 : gnd : : : : +VCCD_PLL1 : 37 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 38 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 : +VCCIO3 : 40 : power : : 2.5V : 3 : +GND : 41 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 : +VCCINT : 45 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 3 : +VCCIO3 : 47 : power : : 2.5V : 3 : +GND : 48 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 52 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 53 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 54 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 55 : : : : 4 : +VCCIO4 : 56 : power : : 2.5V : 4 : +GND : 57 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 : +VCCINT : 61 : power : : 1.2V : : +VCCIO4 : 62 : power : : 2.5V : 4 : +GND : 63 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 65 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 66 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 70 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 73 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 74 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 75 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 77 : : : : 5 : +VCCINT : 78 : power : : 1.2V : : +GND : 79 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 80 : : : : 5 : +VCCIO5 : 81 : power : : 2.5V : 5 : +GND : 82 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 84 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 85 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 86 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 5 : +GND+ : 88 : : : : 5 : +GND+ : 89 : : : : 5 : +GND+ : 90 : : : : 6 : +GND+ : 91 : : : : 6 : +CONF_DONE : 92 : : : : 6 : +VCCIO6 : 93 : power : : 2.5V : 6 : +MSEL0 : 94 : : : : 6 : +GND : 95 : gnd : : : : +MSEL1 : 96 : : : : 6 : +MSEL2 : 97 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 101 : output : 2.5 V : : 6 : N +VCCINT : 102 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 105 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 106 : : : : 6 : +VCCA2 : 107 : power : : 2.5V : : +GNDA2 : 108 : gnd : : : : +VCCD_PLL2 : 109 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 110 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 111 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 112 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 113 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 114 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 115 : : : : 7 : +VCCINT : 116 : power : : 1.2V : : +VCCIO7 : 117 : power : : 2.5V : 7 : +GND : 118 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 119 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 120 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 121 : : : : 7 : +VCCIO7 : 122 : power : : 2.5V : 7 : +GND : 123 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 124 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 125 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 126 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 127 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 128 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 129 : : : : 8 : +VCCIO8 : 130 : power : : 2.5V : 8 : +GND : 131 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 132 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 133 : : : : 8 : +VCCINT : 134 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 135 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 136 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 137 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 138 : : : : 8 : +VCCIO8 : 139 : power : : 2.5V : 8 : +GND : 140 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 141 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 142 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 143 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 144 : : : : 8 : +GND : EPAD : : : : : diff --git a/template/template.qpf b/template/template.qpf new file mode 100755 index 0000000..455ea33 --- /dev/null +++ b/template/template.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 20:32:51 October 18, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "20:32:51 October 18, 2020" + +# Revisions + +PROJECT_REVISION = "template" diff --git a/template/template.qsf b/template/template.qsf new file mode 100755 index 0000000..075c676 --- /dev/null +++ b/template/template.qsf @@ -0,0 +1,118 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 20:32:51 October 18, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# template_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE10E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY template +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:51 OCTOBER 18, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_location_assignment PIN_127 -to HEX_A +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_location_assignment PIN_126 -to HEX_B +set_location_assignment PIN_125 -to HEX_C +set_location_assignment PIN_124 -to HEX_D +set_location_assignment PIN_121 -to HEX_E +set_location_assignment PIN_120 -to HEX_F +set_location_assignment PIN_119 -to HEX_G +set_location_assignment PIN_115 -to HEX_H +set_location_assignment PIN_128 -to HEX[0] +set_location_assignment PIN_129 -to HEX[1] +set_location_assignment PIN_132 -to HEX[2] +set_location_assignment PIN_133 -to HEX[3] +set_location_assignment PIN_135 -to HEX[4] +set_location_assignment PIN_136 -to HEX[5] +set_location_assignment PIN_137 -to HEX[6] +set_location_assignment PIN_138 -to HEX[7] +set_location_assignment PIN_72 -to D[3] +set_location_assignment PIN_73 -to D[4] +set_location_assignment PIN_74 -to D[5] +set_location_assignment PIN_80 -to D[6] +set_location_assignment PIN_83 -to D[7] +set_location_assignment PIN_84 -to D[8] +set_location_assignment PIN_77 -to D[9] +set_location_assignment PIN_76 -to D[10] +set_location_assignment PIN_75 -to D[11] +set_location_assignment PIN_71 -to D[12] +set_location_assignment PIN_70 -to D[13] +set_location_assignment PIN_69 -to D[14] +set_location_assignment PIN_58 -to SW[1] +set_location_assignment PIN_60 -to SW[3] +set_location_assignment PIN_64 -to SW[4] +set_location_assignment PIN_65 -to SW[5] +set_location_assignment PIN_66 -to SW[6] +set_location_assignment PIN_67 -to SW[7] +set_location_assignment PIN_59 -to SW[2] +set_location_assignment PIN_68 -to SW[8] +set_location_assignment PIN_90 -to K[2] +set_location_assignment PIN_91 -to K[3] +set_location_assignment PIN_87 -to K[4] +set_location_assignment PIN_86 -to K[5] +set_location_assignment PIN_141 -to BELL +set_location_assignment PIN_2 -to VGA_R +set_location_assignment PIN_1 -to VGA_G +set_location_assignment PIN_144 -to VGA_B +set_location_assignment PIN_143 -to VGA_VS +set_location_assignment PIN_142 -to VGA_HS +set_location_assignment PIN_3 -to MEM_SDA +set_location_assignment PIN_7 -to MEM_SCK +set_location_assignment PIN_10 -to PS_2_DATA +set_location_assignment PIN_11 -to PS_2_SCK +set_location_assignment PIN_23 -to CLK_50M +set_location_assignment PIN_24 -to CLK_USER +set_location_assignment PIN_114 -to UART_TX +set_location_assignment PIN_113 -to UART_RX +set_location_assignment PIN_101 -to LCD_D[0] +set_location_assignment PIN_103 -to LCD_D[1] +set_location_assignment PIN_104 -to LCD_D[2] +set_location_assignment PIN_105 -to LCD_D[3] +set_location_assignment PIN_106 -to LCD_D[4] +set_location_assignment PIN_110 -to LCD_D[5] +set_location_assignment PIN_111 -to LCD_D[6] +set_location_assignment PIN_112 -to LCD_D[7] +set_location_assignment PIN_85 -to LCD_RS +set_location_assignment PIN_99 -to LCD_WR +set_location_assignment PIN_100 -to LCD_EN \ No newline at end of file diff --git a/template/template.qws b/template/template.qws new file mode 100755 index 0000000..63563b7 Binary files /dev/null and b/template/template.qws differ diff --git a/template/template_assignment_defaults.qdf b/template/template_assignment_defaults.qdf new file mode 100755 index 0000000..67d454d --- /dev/null +++ b/template/template_assignment_defaults.qdf @@ -0,0 +1,808 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 17:03:14 April 10, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?