parent
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commit
861507d867
@ -0,0 +1,25 @@ |
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-- WARNING: Do NOT edit the input and output ports in this file in a text |
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-- editor if you plan to continue editing the block that represents it in |
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-- the Block Editor! File corruption is VERY likely to occur. |
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|
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-- Copyright (C) 2020 Intel Corporation. All rights reserved. |
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-- Your use of Intel Corporation's design tools, logic functions |
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-- and other software and tools, and any partner logic |
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-- functions, and any output files from any of the foregoing |
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-- (including device programming or simulation files), and any |
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-- associated documentation or information are expressly subject |
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-- to the terms and conditions of the Intel Program License |
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-- Subscription Agreement, the Intel Quartus Prime License Agreement, |
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-- the Intel FPGA IP License Agreement, or other applicable license |
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-- agreement, including, without limitation, that your use is for |
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-- the sole purpose of programming logic devices manufactured by |
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-- Intel and sold by Intel or its authorized distributors. Please |
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-- refer to the applicable agreement for further details, at |
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-- https://fpgasoftware.intel.com/eula. |
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|
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|
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-- Generated by Quartus Prime Version 20.1 (Build Build 720 11/11/2020) |
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-- Created on Sat Apr 24 03:39:58 2021 |
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|
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FUNCTION 7seg_driver (D[3..0]) |
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RETURNS (SEG[6..0]); |
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@ -0,0 +1,23 @@ |
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subdesign 7seg_driver (D[3..0]: input = VCC; SEG[6..0]: output;) |
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begin |
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|
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case d[] is |
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when 0 => SEG[6..0] = b"0000001"; |
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when 1 => SEG[6..0] = b"1001111"; |
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when 2 => SEG[6..0] = b"0010010"; |
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when 3 => SEG[6..0] = b"0000110"; |
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when 4 => SEG[6..0] = b"1001100"; |
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when 5 => SEG[6..0] = b"0100100"; |
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when 6 => SEG[6..0] = b"0100000"; |
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when 7 => SEG[6..0] = b"0001111"; |
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when 8 => SEG[6..0] = b"0000000"; |
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when 9 => SEG[6..0] = b"0000100"; |
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when 10 => SEG[6..0] = b"0001000"; |
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when 11 => SEG[6..0] = b"1100000"; |
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when 12 => SEG[6..0] = b"0110001"; |
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when 13 => SEG[6..0] = b"1000010"; |
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when 14 => SEG[6..0] = b"0110000"; |
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when 15 => SEG[6..0] = b"0111000"; |
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when others => SEG[6..0] = VCC; |
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end case; |
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end; |
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@ -0,0 +1,25 @@ |
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subdesign 7seg_driver (DP, D[0..3]: input = VCC; SEG[0..7]: output;) |
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begin |
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|
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SEG[7] = DP; |
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|
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case d[] is |
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when 0 => SEG[0..6] = b"0000001"; |
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when 1 => SEG[0..6] = b"1001111"; |
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when 2 => SEG[0..6] = b"0010010"; |
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when 3 => SEG[0..6] = b"0000110"; |
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when 4 => SEG[0..6] = b"1001100"; |
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when 5 => SEG[0..6] = b"0100100"; |
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when 6 => SEG[0..6] = b"0100000"; |
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when 7 => SEG[0..6] = b"0001111"; |
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when 8 => SEG[0..6] = b"0000000"; |
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when 9 => SEG[0..6] = b"0000100"; |
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when 10 => SEG[0..6] = b"0001000"; |
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when 11 => SEG[0..6] = b"1100000"; |
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when 12 => SEG[0..6] = b"0110001"; |
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when 13 => SEG[0..6] = b"1000010"; |
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when 14 => SEG[0..6] = b"0110000"; |
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when 15 => SEG[0..6] = b"0111000"; |
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when others => SEG[0..6] = VCC; |
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end case; |
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end; |
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@ -0,0 +1,58 @@ |
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/* |
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WARNING: Do NOT edit the input and output ports in this file in a text |
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editor if you plan to continue editing the block that represents it in |
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the Block Editor! File corruption is VERY likely to occur. |
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*/ |
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/* |
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Copyright (C) 2020 Intel Corporation. All rights reserved. |
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Your use of Intel Corporation's design tools, logic functions |
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and other software and tools, and any partner logic |
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functions, and any output files from any of the foregoing |
||||
(including device programming or simulation files), and any |
||||
associated documentation or information are expressly subject |
||||
to the terms and conditions of the Intel Program License |
||||
Subscription Agreement, the Intel Quartus Prime License Agreement, |
||||
the Intel FPGA IP License Agreement, or other applicable license |
||||
agreement, including, without limitation, that your use is for |
||||
the sole purpose of programming logic devices manufactured by |
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Intel and sold by Intel or its authorized distributors. Please |
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refer to the applicable agreement for further details, at |
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https://fpgasoftware.intel.com/eula. |
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*/ |
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(header "symbol" (version "1.1")) |
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(symbol |
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(rect 16 16 208 96) |
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(text "LED_7seg_driver" (rect 5 0 79 12)(font "Arial" )) |
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(text "inst" (rect 8 64 20 76)(font "Arial" )) |
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(port |
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(pt 0 32) |
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(input) |
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(text "D[0..7][0..4]" (rect 0 0 48 12)(font "Arial" )) |
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(text "D[0..7][0..4]" (rect 21 27 69 39)(font "Arial" )) |
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(line (pt 0 32)(pt 16 32)(line_width 3)) |
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) |
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(port |
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(pt 0 48) |
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(input) |
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(text "clk" (rect 0 0 10 12)(font "Arial" )) |
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(text "clk" (rect 21 43 31 55)(font "Arial" )) |
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(line (pt 0 48)(pt 16 48)(line_width 1)) |
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) |
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(port |
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(pt 192 32) |
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(output) |
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(text "dig[0..7]" (rect 0 0 30 12)(font "Arial" )) |
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(text "dig[0..7]" (rect 141 27 171 39)(font "Arial" )) |
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(line (pt 192 32)(pt 176 32)(line_width 3)) |
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) |
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(port |
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(pt 192 48) |
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(output) |
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(text "SEG[6..0]" (rect 0 0 40 12)(font "Arial" )) |
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(text "SEG[6..0]" (rect 131 43 171 55)(font "Arial" )) |
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(line (pt 192 48)(pt 176 48)(line_width 3)) |
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) |
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(drawing |
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(rectangle (rect 16 16 176 64)(line_width 1)) |
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) |
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) |
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@ -0,0 +1,7 @@ |
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224941420 ""} |
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224941421 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:21 2021 " "Processing started: Sat Apr 24 03:42:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224941421 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619224941421 ""} |
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off template -c template " "Command: quartus_asm --read_settings_files=off --write_settings_files=off template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619224941421 ""} |
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619224941606 ""} |
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{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619224941873 ""} |
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619224941888 ""} |
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{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "351 " "Peak virtual memory: 351 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:21 2021 " "Processing ended: Sat Apr 24 03:42:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224941963 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619224941963 ""} |
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@ -0,0 +1,5 @@ |
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<?xml version="1.0" ?> |
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<LOG_ROOT> |
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<PROJECT NAME="template"> |
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</PROJECT> |
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</LOG_ROOT> |
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@ -0,0 +1,59 @@ |
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v1 |
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IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, |
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IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, |
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IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, |
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IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, |
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IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, |
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IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, |
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IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, |
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IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, |
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IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, |
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IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, |
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IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, |
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IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, |
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IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, |
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IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, |
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IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, |
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IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, |
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IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, |
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IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, |
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IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, |
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IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, |
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IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, |
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IO_RULES_MATRIX,Total Pass,0;17;17;0;0;17;17;0;0;0;0;0;0;15;0;0;0;2;15;0;2;0;0;15;0;17;17;17;0;0, |
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IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, |
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IO_RULES_MATRIX,Total Inapplicable,17;0;0;17;17;0;0;17;17;17;17;17;17;2;17;17;17;15;2;17;15;17;17;2;17;0;0;0;17;17, |
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IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, |
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IO_RULES_MATRIX,HEX[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,HEX[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,HEX[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,HEX[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,HEX[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,HEX[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,HEX[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,HEX[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,SEG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,SEG[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,SEG[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,SEG[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,SEG[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,SEG[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,SEG[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
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IO_RULES_MATRIX,K[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
||||
IO_RULES_MATRIX,K[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, |
||||
IO_RULES_SUMMARY,Total I/O Rules,30, |
||||
IO_RULES_SUMMARY,Number of I/O Rules Passed,12, |
||||
IO_RULES_SUMMARY,Number of I/O Rules Failed,0, |
||||
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, |
||||
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, |
||||
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@ -0,0 +1,3 @@ |
||||
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
Version_Index = 520278016 |
||||
Creation_Time = Fri Apr 23 19:24:53 2021 |
||||
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@ -0,0 +1,755 @@ |
||||
|template |
||||
HEX[7] <= LED_7seg_driver:inst.dig[7] |
||||
HEX[6] <= LED_7seg_driver:inst.dig[6] |
||||
HEX[5] <= LED_7seg_driver:inst.dig[5] |
||||
HEX[4] <= LED_7seg_driver:inst.dig[4] |
||||
HEX[3] <= LED_7seg_driver:inst.dig[3] |
||||
HEX[2] <= LED_7seg_driver:inst.dig[2] |
||||
HEX[1] <= LED_7seg_driver:inst.dig[1] |
||||
HEX[0] <= LED_7seg_driver:inst.dig[0] |
||||
K[2] => LED_7seg_driver:inst.clk |
||||
K[3] => test:inst4.test |
||||
SEG[6] <= LED_7seg_driver:inst.SEG[0] |
||||
SEG[5] <= LED_7seg_driver:inst.SEG[1] |
||||
SEG[4] <= LED_7seg_driver:inst.SEG[2] |
||||
SEG[3] <= LED_7seg_driver:inst.SEG[3] |
||||
SEG[2] <= LED_7seg_driver:inst.SEG[4] |
||||
SEG[1] <= LED_7seg_driver:inst.SEG[5] |
||||
SEG[0] <= LED_7seg_driver:inst.SEG[6] |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst |
||||
D[7][3] => in_buf[7][3].DATAIN |
||||
D[7][2] => in_buf[7][2].DATAIN |
||||
D[7][1] => in_buf[7][1].DATAIN |
||||
D[7][0] => in_buf[7][0].DATAIN |
||||
D[6][3] => in_buf[6][3].DATAIN |
||||
D[6][2] => in_buf[6][2].DATAIN |
||||
D[6][1] => in_buf[6][1].DATAIN |
||||
D[6][0] => in_buf[6][0].DATAIN |
||||
D[5][3] => in_buf[5][3].DATAIN |
||||
D[5][2] => in_buf[5][2].DATAIN |
||||
D[5][1] => in_buf[5][1].DATAIN |
||||
D[5][0] => in_buf[5][0].DATAIN |
||||
D[4][3] => in_buf[4][3].DATAIN |
||||
D[4][2] => in_buf[4][2].DATAIN |
||||
D[4][1] => in_buf[4][1].DATAIN |
||||
D[4][0] => in_buf[4][0].DATAIN |
||||
D[3][3] => in_buf[3][3].DATAIN |
||||
D[3][2] => in_buf[3][2].DATAIN |
||||
D[3][1] => in_buf[3][1].DATAIN |
||||
D[3][0] => in_buf[3][0].DATAIN |
||||
D[2][3] => in_buf[2][3].DATAIN |
||||
D[2][2] => in_buf[2][2].DATAIN |
||||
D[2][1] => in_buf[2][1].DATAIN |
||||
D[2][0] => in_buf[2][0].DATAIN |
||||
D[1][3] => in_buf[1][3].DATAIN |
||||
D[1][2] => in_buf[1][2].DATAIN |
||||
D[1][1] => in_buf[1][1].DATAIN |
||||
D[1][0] => in_buf[1][0].DATAIN |
||||
D[0][3] => in_buf[0][3].DATAIN |
||||
D[0][2] => in_buf[0][2].DATAIN |
||||
D[0][1] => in_buf[0][1].DATAIN |
||||
D[0][0] => in_buf[0][0].DATAIN |
||||
clk => in_buf[7][3].CLK |
||||
clk => in_buf[7][2].CLK |
||||
clk => in_buf[7][1].CLK |
||||
clk => in_buf[7][0].CLK |
||||
clk => in_buf[6][3].CLK |
||||
clk => in_buf[6][2].CLK |
||||
clk => in_buf[6][1].CLK |
||||
clk => in_buf[6][0].CLK |
||||
clk => in_buf[5][3].CLK |
||||
clk => in_buf[5][2].CLK |
||||
clk => in_buf[5][1].CLK |
||||
clk => in_buf[5][0].CLK |
||||
clk => in_buf[4][3].CLK |
||||
clk => in_buf[4][2].CLK |
||||
clk => in_buf[4][1].CLK |
||||
clk => in_buf[4][0].CLK |
||||
clk => in_buf[3][3].CLK |
||||
clk => in_buf[3][2].CLK |
||||
clk => in_buf[3][1].CLK |
||||
clk => in_buf[3][0].CLK |
||||
clk => in_buf[2][3].CLK |
||||
clk => in_buf[2][2].CLK |
||||
clk => in_buf[2][1].CLK |
||||
clk => in_buf[2][0].CLK |
||||
clk => in_buf[1][3].CLK |
||||
clk => in_buf[1][2].CLK |
||||
clk => in_buf[1][1].CLK |
||||
clk => in_buf[1][0].CLK |
||||
clk => in_buf[0][3].CLK |
||||
clk => in_buf[0][2].CLK |
||||
clk => in_buf[0][1].CLK |
||||
clk => in_buf[0][0].CLK |
||||
clk => switcher[3].CLK |
||||
clk => switcher[2].CLK |
||||
clk => switcher[1].CLK |
||||
clk => switcher[0].CLK |
||||
dig[7] <= dig[7].DB_MAX_OUTPUT_PORT_TYPE |
||||
dig[6] <= dig[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
dig[5] <= dig[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
dig[4] <= dig[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
dig[3] <= dig[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
dig[2] <= dig[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
dig[1] <= dig[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
dig[0] <= dig[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst|7seg_driver:$00000 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~2.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~4.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~6.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[3]~8.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~9.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~11.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~13.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~15.IN3 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[4]~3.IN2 |
||||
D[1] => SEG[2]~4.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~7.IN2 |
||||
D[1] => SEG[3]~8.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[3]~10.IN2 |
||||
D[1] => SEG[6]~11.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~14.IN2 |
||||
D[1] => SEG[5]~15.IN2 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[6]~5.IN1 |
||||
D[2] => SEG[5]~6.IN1 |
||||
D[2] => SEG[5]~7.IN1 |
||||
D[2] => SEG[3]~8.IN1 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[5]~12.IN1 |
||||
D[2] => SEG[6]~13.IN1 |
||||
D[2] => SEG[5]~14.IN1 |
||||
D[2] => SEG[5]~15.IN1 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => SEG[2]~9.IN0 |
||||
D[3] => SEG[3]~10.IN0 |
||||
D[3] => SEG[6]~11.IN0 |
||||
D[3] => SEG[5]~12.IN0 |
||||
D[3] => SEG[6]~13.IN0 |
||||
D[3] => SEG[5]~14.IN0 |
||||
D[3] => SEG[5]~15.IN0 |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst|7seg_driver:$00002 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~2.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~4.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~6.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[3]~8.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~9.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~11.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~13.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~15.IN3 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[4]~3.IN2 |
||||
D[1] => SEG[2]~4.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~7.IN2 |
||||
D[1] => SEG[3]~8.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[3]~10.IN2 |
||||
D[1] => SEG[6]~11.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~14.IN2 |
||||
D[1] => SEG[5]~15.IN2 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[6]~5.IN1 |
||||
D[2] => SEG[5]~6.IN1 |
||||
D[2] => SEG[5]~7.IN1 |
||||
D[2] => SEG[3]~8.IN1 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[5]~12.IN1 |
||||
D[2] => SEG[6]~13.IN1 |
||||
D[2] => SEG[5]~14.IN1 |
||||
D[2] => SEG[5]~15.IN1 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => SEG[2]~9.IN0 |
||||
D[3] => SEG[3]~10.IN0 |
||||
D[3] => SEG[6]~11.IN0 |
||||
D[3] => SEG[5]~12.IN0 |
||||
D[3] => SEG[6]~13.IN0 |
||||
D[3] => SEG[5]~14.IN0 |
||||
D[3] => SEG[5]~15.IN0 |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst|7seg_driver:$00004 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~2.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~4.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~6.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[3]~8.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~9.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~11.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~13.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~15.IN3 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[4]~3.IN2 |
||||
D[1] => SEG[2]~4.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~7.IN2 |
||||
D[1] => SEG[3]~8.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[3]~10.IN2 |
||||
D[1] => SEG[6]~11.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~14.IN2 |
||||
D[1] => SEG[5]~15.IN2 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[6]~5.IN1 |
||||
D[2] => SEG[5]~6.IN1 |
||||
D[2] => SEG[5]~7.IN1 |
||||
D[2] => SEG[3]~8.IN1 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[5]~12.IN1 |
||||
D[2] => SEG[6]~13.IN1 |
||||
D[2] => SEG[5]~14.IN1 |
||||
D[2] => SEG[5]~15.IN1 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => SEG[2]~9.IN0 |
||||
D[3] => SEG[3]~10.IN0 |
||||
D[3] => SEG[6]~11.IN0 |
||||
D[3] => SEG[5]~12.IN0 |
||||
D[3] => SEG[6]~13.IN0 |
||||
D[3] => SEG[5]~14.IN0 |
||||
D[3] => SEG[5]~15.IN0 |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst|7seg_driver:$00006 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~2.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~4.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~6.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[3]~8.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~9.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~11.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~13.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~15.IN3 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[4]~3.IN2 |
||||
D[1] => SEG[2]~4.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~7.IN2 |
||||
D[1] => SEG[3]~8.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[3]~10.IN2 |
||||
D[1] => SEG[6]~11.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~14.IN2 |
||||
D[1] => SEG[5]~15.IN2 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[6]~5.IN1 |
||||
D[2] => SEG[5]~6.IN1 |
||||
D[2] => SEG[5]~7.IN1 |
||||
D[2] => SEG[3]~8.IN1 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[5]~12.IN1 |
||||
D[2] => SEG[6]~13.IN1 |
||||
D[2] => SEG[5]~14.IN1 |
||||
D[2] => SEG[5]~15.IN1 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => SEG[2]~9.IN0 |
||||
D[3] => SEG[3]~10.IN0 |
||||
D[3] => SEG[6]~11.IN0 |
||||
D[3] => SEG[5]~12.IN0 |
||||
D[3] => SEG[6]~13.IN0 |
||||
D[3] => SEG[5]~14.IN0 |
||||
D[3] => SEG[5]~15.IN0 |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst|7seg_driver:$00008 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~2.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~4.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~6.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[3]~8.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~9.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~11.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~13.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~15.IN3 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[4]~3.IN2 |
||||
D[1] => SEG[2]~4.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~7.IN2 |
||||
D[1] => SEG[3]~8.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[3]~10.IN2 |
||||
D[1] => SEG[6]~11.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~14.IN2 |
||||
D[1] => SEG[5]~15.IN2 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[6]~5.IN1 |
||||
D[2] => SEG[5]~6.IN1 |
||||
D[2] => SEG[5]~7.IN1 |
||||
D[2] => SEG[3]~8.IN1 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[5]~12.IN1 |
||||
D[2] => SEG[6]~13.IN1 |
||||
D[2] => SEG[5]~14.IN1 |
||||
D[2] => SEG[5]~15.IN1 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => SEG[2]~9.IN0 |
||||
D[3] => SEG[3]~10.IN0 |
||||
D[3] => SEG[6]~11.IN0 |
||||
D[3] => SEG[5]~12.IN0 |
||||
D[3] => SEG[6]~13.IN0 |
||||
D[3] => SEG[5]~14.IN0 |
||||
D[3] => SEG[5]~15.IN0 |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst|7seg_driver:$00010 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~2.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~4.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~6.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[3]~8.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~9.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~11.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~13.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~15.IN3 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[4]~3.IN2 |
||||
D[1] => SEG[2]~4.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~7.IN2 |
||||
D[1] => SEG[3]~8.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[3]~10.IN2 |
||||
D[1] => SEG[6]~11.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~14.IN2 |
||||
D[1] => SEG[5]~15.IN2 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[6]~5.IN1 |
||||
D[2] => SEG[5]~6.IN1 |
||||
D[2] => SEG[5]~7.IN1 |
||||
D[2] => SEG[3]~8.IN1 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[5]~12.IN1 |
||||
D[2] => SEG[6]~13.IN1 |
||||
D[2] => SEG[5]~14.IN1 |
||||
D[2] => SEG[5]~15.IN1 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => SEG[2]~9.IN0 |
||||
D[3] => SEG[3]~10.IN0 |
||||
D[3] => SEG[6]~11.IN0 |
||||
D[3] => SEG[5]~12.IN0 |
||||
D[3] => SEG[6]~13.IN0 |
||||
D[3] => SEG[5]~14.IN0 |
||||
D[3] => SEG[5]~15.IN0 |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst|7seg_driver:$00012 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~2.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~4.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~6.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[3]~8.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~9.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~11.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~13.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~15.IN3 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[4]~3.IN2 |
||||
D[1] => SEG[2]~4.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~7.IN2 |
||||
D[1] => SEG[3]~8.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[3]~10.IN2 |
||||
D[1] => SEG[6]~11.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~14.IN2 |
||||
D[1] => SEG[5]~15.IN2 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[6]~5.IN1 |
||||
D[2] => SEG[5]~6.IN1 |
||||
D[2] => SEG[5]~7.IN1 |
||||
D[2] => SEG[3]~8.IN1 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[5]~12.IN1 |
||||
D[2] => SEG[6]~13.IN1 |
||||
D[2] => SEG[5]~14.IN1 |
||||
D[2] => SEG[5]~15.IN1 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => SEG[2]~9.IN0 |
||||
D[3] => SEG[3]~10.IN0 |
||||
D[3] => SEG[6]~11.IN0 |
||||
D[3] => SEG[5]~12.IN0 |
||||
D[3] => SEG[6]~13.IN0 |
||||
D[3] => SEG[5]~14.IN0 |
||||
D[3] => SEG[5]~15.IN0 |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|LED_7seg_driver:inst|7seg_driver:$00014 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~2.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~4.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~6.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[3]~8.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[2]~9.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~11.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[6]~13.IN3 |
||||
D[0] => _.IN0 |
||||
D[0] => SEG[5]~15.IN3 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[4]~3.IN2 |
||||
D[1] => SEG[2]~4.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~7.IN2 |
||||
D[1] => SEG[3]~8.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[3]~10.IN2 |
||||
D[1] => SEG[6]~11.IN2 |
||||
D[1] => _.IN0 |
||||
D[1] => _.IN0 |
||||
D[1] => SEG[5]~14.IN2 |
||||
D[1] => SEG[5]~15.IN2 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[6]~5.IN1 |
||||
D[2] => SEG[5]~6.IN1 |
||||
D[2] => SEG[5]~7.IN1 |
||||
D[2] => SEG[3]~8.IN1 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => _.IN0 |
||||
D[2] => SEG[5]~12.IN1 |
||||
D[2] => SEG[6]~13.IN1 |
||||
D[2] => SEG[5]~14.IN1 |
||||
D[2] => SEG[5]~15.IN1 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => _.IN0 |
||||
D[3] => SEG[2]~9.IN0 |
||||
D[3] => SEG[3]~10.IN0 |
||||
D[3] => SEG[6]~11.IN0 |
||||
D[3] => SEG[5]~12.IN0 |
||||
D[3] => SEG[6]~13.IN0 |
||||
D[3] => SEG[5]~14.IN0 |
||||
D[3] => SEG[5]~15.IN0 |
||||
SEG[0] <= SEG[0].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[1] <= SEG[1].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[2] <= SEG[2].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[3] <= SEG[3].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[4] <= SEG[4].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[5] <= SEG[5].DB_MAX_OUTPUT_PORT_TYPE |
||||
SEG[6] <= SEG[6].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
|template|test:inst4 |
||||
test => _.IN0 |
||||
test => number[0][0].IN0 |
||||
test => number[1][1].IN0 |
||||
test => number[2][1].IN0 |
||||
test => number[2][0].IN0 |
||||
test => number[3][2].IN0 |
||||
test => number[4][2].IN0 |
||||
test => number[4][0].IN0 |
||||
test => number[5][2].IN0 |
||||
test => number[5][1].IN0 |
||||
test => number[6][2].IN0 |
||||
test => number[6][1].IN0 |
||||
test => number[6][0].IN0 |
||||
test => number[7][3].IN0 |
||||
number[0][0] <= number[0][0].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[0][1] <= number[0][1].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[0][2] <= number[0][2].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[0][3] <= number[0][3].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[0][4] <= number[0][4].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[1][0] <= number[1][0].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[1][1] <= number[1][1].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[1][2] <= number[1][2].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[1][3] <= number[1][3].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[1][4] <= number[1][4].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[2][0] <= number[2][0].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[2][1] <= number[2][1].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[2][2] <= number[2][2].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[2][3] <= number[2][3].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[2][4] <= number[2][4].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[3][0] <= number[3][0].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[3][1] <= number[3][1].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[3][2] <= number[3][2].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[3][3] <= number[3][3].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[3][4] <= number[3][4].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[4][0] <= number[4][0].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[4][1] <= number[4][1].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[4][2] <= number[4][2].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[4][3] <= number[4][3].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[4][4] <= number[4][4].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[5][0] <= number[5][0].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[5][1] <= number[5][1].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[5][2] <= number[5][2].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[5][3] <= number[5][3].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[5][4] <= number[5][4].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[6][0] <= number[6][0].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[6][1] <= number[6][1].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[6][2] <= number[6][2].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[6][3] <= number[6][3].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[6][4] <= number[6][4].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[7][0] <= number[7][0].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[7][1] <= number[7][1].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[7][2] <= number[7][2].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[7][3] <= number[7][3].DB_MAX_OUTPUT_PORT_TYPE |
||||
number[7][4] <= number[7][4].DB_MAX_OUTPUT_PORT_TYPE |
||||
|
||||
|
||||
Binary file not shown.
@ -0,0 +1,178 @@ |
||||
<TABLE> |
||||
<TR bgcolor="#C0C0C0"> |
||||
<TH>Hierarchy</TH> |
||||
<TH>Input</TH> |
||||
<TH>Constant Input</TH> |
||||
<TH>Unused Input</TH> |
||||
<TH>Floating Input</TH> |
||||
<TH>Output</TH> |
||||
<TH>Constant Output</TH> |
||||
<TH>Unused Output</TH> |
||||
<TH>Floating Output</TH> |
||||
<TH>Bidir</TH> |
||||
<TH>Constant Bidir</TH> |
||||
<TH>Unused Bidir</TH> |
||||
<TH>Input only Bidir</TH> |
||||
<TH>Output only Bidir</TH> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst4</TD> |
||||
<TD >1</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >40</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst|$00014</TD> |
||||
<TD >4</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >7</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst|$00012</TD> |
||||
<TD >4</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >7</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst|$00010</TD> |
||||
<TD >4</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >7</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst|$00008</TD> |
||||
<TD >4</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >7</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst|$00006</TD> |
||||
<TD >4</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >7</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
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<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst|$00004</TD> |
||||
<TD >4</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >7</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst|$00002</TD> |
||||
<TD >4</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >7</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst|$00000</TD> |
||||
<TD >4</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >7</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
<TR > |
||||
<TD >inst</TD> |
||||
<TD >33</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >15</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
<TD >0</TD> |
||||
</TR> |
||||
</TABLE> |
||||
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||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Legal Partition Candidates ; |
||||
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ |
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; |
||||
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ |
||||
; inst4 ; 1 ; 0 ; 0 ; 0 ; 40 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
||||
; inst|$00014 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
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; inst|$00012 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
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; inst|$00010 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
||||
; inst|$00008 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
||||
; inst|$00006 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
||||
; inst|$00004 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
||||
; inst|$00002 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
||||
; inst|$00000 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
||||
; inst ; 33 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
||||
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ |
||||
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v1 |
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DONE |
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||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619224942770 ""} |
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619224942771 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 03:42:22 2021 " "Processing started: Sat Apr 24 03:42:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619224942771 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224942771 ""} |
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta template -c template " "Command: quartus_sta template -c template" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224942771 ""} |
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1619224942808 ""} |
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1619224942881 ""} |
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1619224942881 ""} |
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224942949 ""} |
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224942950 ""} |
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "template.sdc " "Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1619224943126 ""} |
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943126 ""} |
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name K\[2\] K\[2\] " "create_clock -period 1.000 -name K\[2\] K\[2\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1619224943127 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943127 ""} |
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943128 ""} |
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943128 ""} |
||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1619224943129 ""} |
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1619224943132 ""} |
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1619224943137 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1619224943137 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.356 " "Worst-case setup slack is -0.356" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.356 -0.706 K\[2\] " " -0.356 -0.706 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943138 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943138 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.453 " "Worst-case hold slack is 0.453" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.453 0.000 K\[2\] " " 0.453 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943139 ""} |
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943140 ""} |
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943140 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -10.435 K\[2\] " " -3.000 -10.435 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943141 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943141 ""} |
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619224943156 ""} |
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1619224943178 ""} |
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1619224943365 ""} |
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943403 ""} |
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1619224943404 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1619224943404 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.219 " "Worst-case setup slack is -0.219" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.219 -0.412 K\[2\] " " -0.219 -0.412 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943405 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943405 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 K\[2\] " " 0.401 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943406 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943406 ""} |
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943407 ""} |
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943408 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -10.435 K\[2\] " " -3.000 -10.435 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943409 ""} |
||||
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1619224943425 ""} |
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1619224943553 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.404 " "Worst-case setup slack is 0.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.404 0.000 K\[2\] " " 0.404 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943554 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943554 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.187 " "Worst-case hold slack is 0.187" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.187 0.000 K\[2\] " " 0.187 0.000 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943556 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943556 ""} |
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943557 ""} |
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1619224943558 ""} |
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1619224943558 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1619224943558 ""} |
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -8.315 K\[2\] " " -3.000 -8.315 K\[2\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1619224943559 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1619224943559 ""} |
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619224943937 ""} |
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1619224943937 ""} |
||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "444 " "Peak virtual memory: 444 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619224943955 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 03:42:23 2021 " "Processing ended: Sat Apr 24 03:42:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619224943955 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619224943955 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619224943955 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1619224943955 ""} |
||||
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@ -0,0 +1,6 @@ |
||||
start_full_compilation:s:00:00:18 |
||||
start_analysis_synthesis:s:00:00:10-start_full_compilation |
||||
start_analysis_elaboration:s-start_full_compilation |
||||
start_fitter:s:00:00:04-start_full_compilation |
||||
start_assembler:s:00:00:02-start_full_compilation |
||||
start_timing_analyzer:s:00:00:02-start_full_compilation |
||||
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@ -0,0 +1,57 @@ |
||||
{ |
||||
"partitions" : [ |
||||
{ |
||||
"name" : "Top", |
||||
"pins" : [ |
||||
{ |
||||
"name" : "HEX[5]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "HEX[6]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "HEX[7]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "SEG[0]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "SEG[1]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "SEG[2]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "SEG[3]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "SEG[4]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "SEG[5]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "SEG[6]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "K[2]", |
||||
"strict" : false |
||||
}, |
||||
{ |
||||
"name" : "K[3]", |
||||
"strict" : false |
||||
} |
||||
] |
||||
} |
||||
] |
||||
} |
||||
@ -0,0 +1,11 @@ |
||||
This folder contains data for incremental compilation. |
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition. |
||||
As long as this folder is preserved, incremental compilation results from earlier compiles |
||||
can be re-used. To perform a clean compilation from source files for all partitions, both |
||||
the db and incremental_db folder should be removed. |
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition. |
||||
As long as this folder is preserved, imported partitions will be automatically re-imported |
||||
when the db or incremental_db/compiled_partitions folders are removed. |
||||
|
||||
@ -0,0 +1,3 @@ |
||||
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
Version_Index = 520278016 |
||||
Creation_Time = Fri Apr 23 19:27:34 2021 |
||||
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@ -0,0 +1 @@ |
||||
v1 |
||||
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@ -0,0 +1 @@ |
||||
c5eb7f6cdd530884c3b884e0a3668ea4 |
||||
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Binary file not shown.
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@ -0,0 +1,92 @@ |
||||
Assembler report for template |
||||
Sat Apr 24 03:42:21 2021 |
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
|
||||
|
||||
--------------------- |
||||
; Table of Contents ; |
||||
--------------------- |
||||
1. Legal Notice |
||||
2. Assembler Summary |
||||
3. Assembler Settings |
||||
4. Assembler Generated Files |
||||
5. Assembler Device Options: template.sof |
||||
6. Assembler Messages |
||||
|
||||
|
||||
|
||||
---------------- |
||||
; Legal Notice ; |
||||
---------------- |
||||
Copyright (C) 2020 Intel Corporation. All rights reserved. |
||||
Your use of Intel Corporation's design tools, logic functions |
||||
and other software and tools, and any partner logic |
||||
functions, and any output files from any of the foregoing |
||||
(including device programming or simulation files), and any |
||||
associated documentation or information are expressly subject |
||||
to the terms and conditions of the Intel Program License |
||||
Subscription Agreement, the Intel Quartus Prime License Agreement, |
||||
the Intel FPGA IP License Agreement, or other applicable license |
||||
agreement, including, without limitation, that your use is for |
||||
the sole purpose of programming logic devices manufactured by |
||||
Intel and sold by Intel or its authorized distributors. Please |
||||
refer to the applicable agreement for further details, at |
||||
https://fpgasoftware.intel.com/eula. |
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------+ |
||||
; Assembler Summary ; |
||||
+-----------------------+---------------------------------------+ |
||||
; Assembler Status ; Successful - Sat Apr 24 03:42:21 2021 ; |
||||
; Revision Name ; template ; |
||||
; Top-level Entity Name ; template ; |
||||
; Family ; Cyclone IV E ; |
||||
; Device ; EP4CE10E22C8 ; |
||||
+-----------------------+---------------------------------------+ |
||||
|
||||
|
||||
+----------------------------------+ |
||||
; Assembler Settings ; |
||||
+--------+---------+---------------+ |
||||
; Option ; Setting ; Default Value ; |
||||
+--------+---------+---------------+ |
||||
|
||||
|
||||
+-----------------------------------------------------------------+ |
||||
; Assembler Generated Files ; |
||||
+-----------------------------------------------------------------+ |
||||
; File Name ; |
||||
+-----------------------------------------------------------------+ |
||||
; /home/zen/a-c4e6e10_exemple/AHDL_test/output_files/template.sof ; |
||||
+-----------------------------------------------------------------+ |
||||
|
||||
|
||||
+----------------------------------------+ |
||||
; Assembler Device Options: template.sof ; |
||||
+----------------+-----------------------+ |
||||
; Option ; Setting ; |
||||
+----------------+-----------------------+ |
||||
; JTAG usercode ; 0x00095D12 ; |
||||
; Checksum ; 0x00095D12 ; |
||||
+----------------+-----------------------+ |
||||
|
||||
|
||||
+--------------------+ |
||||
; Assembler Messages ; |
||||
+--------------------+ |
||||
Info: ******************************************************************* |
||||
Info: Running Quartus Prime Assembler |
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
Info: Processing started: Sat Apr 24 03:42:21 2021 |
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off template -c template |
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. |
||||
Info (115031): Writing out detailed assembly data for power analysis |
||||
Info (115030): Assembler is generating device programming files |
||||
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning |
||||
Info: Peak virtual memory: 351 megabytes |
||||
Info: Processing ended: Sat Apr 24 03:42:21 2021 |
||||
Info: Elapsed time: 00:00:00 |
||||
Info: Total CPU time (on all processors): 00:00:01 |
||||
|
||||
|
||||
@ -0,0 +1 @@ |
||||
Sat Apr 24 03:42:24 2021 |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,8 @@ |
||||
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments |
||||
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments |
||||
Extra Info (176236): Started Fast Input/Output/OE register processing |
||||
Extra Info (176237): Finished Fast Input/Output/OE register processing |
||||
Extra Info (176238): Start inferring scan chains for DSP blocks |
||||
Extra Info (176239): Inferring scan chains for DSP blocks is complete |
||||
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density |
||||
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks |
||||
@ -0,0 +1,16 @@ |
||||
Fitter Status : Successful - Sat Apr 24 03:42:20 2021 |
||||
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
Revision Name : template |
||||
Top-level Entity Name : template |
||||
Family : Cyclone IV E |
||||
Device : EP4CE10E22C8 |
||||
Timing Models : Final |
||||
Total logic elements : 16 / 10,320 ( < 1 % ) |
||||
Total combinational functions : 15 / 10,320 ( < 1 % ) |
||||
Dedicated logic registers : 5 / 10,320 ( < 1 % ) |
||||
Total registers : 5 |
||||
Total pins : 17 / 92 ( 18 % ) |
||||
Total virtual pins : 0 |
||||
Total memory bits : 0 / 423,936 ( 0 % ) |
||||
Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % ) |
||||
Total PLLs : 0 / 2 ( 0 % ) |
||||
@ -0,0 +1,124 @@ |
||||
Flow report for template |
||||
Sat Apr 24 03:42:23 2021 |
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
|
||||
|
||||
--------------------- |
||||
; Table of Contents ; |
||||
--------------------- |
||||
1. Legal Notice |
||||
2. Flow Summary |
||||
3. Flow Settings |
||||
4. Flow Non-Default Global Settings |
||||
5. Flow Elapsed Time |
||||
6. Flow OS Summary |
||||
7. Flow Log |
||||
8. Flow Messages |
||||
9. Flow Suppressed Messages |
||||
|
||||
|
||||
|
||||
---------------- |
||||
; Legal Notice ; |
||||
---------------- |
||||
Copyright (C) 2020 Intel Corporation. All rights reserved. |
||||
Your use of Intel Corporation's design tools, logic functions |
||||
and other software and tools, and any partner logic |
||||
functions, and any output files from any of the foregoing |
||||
(including device programming or simulation files), and any |
||||
associated documentation or information are expressly subject |
||||
to the terms and conditions of the Intel Program License |
||||
Subscription Agreement, the Intel Quartus Prime License Agreement, |
||||
the Intel FPGA IP License Agreement, or other applicable license |
||||
agreement, including, without limitation, that your use is for |
||||
the sole purpose of programming logic devices manufactured by |
||||
Intel and sold by Intel or its authorized distributors. Please |
||||
refer to the applicable agreement for further details, at |
||||
https://fpgasoftware.intel.com/eula. |
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------+ |
||||
; Flow Summary ; |
||||
+------------------------------------+---------------------------------------------+ |
||||
; Flow Status ; Successful - Sat Apr 24 03:42:21 2021 ; |
||||
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; |
||||
; Revision Name ; template ; |
||||
; Top-level Entity Name ; template ; |
||||
; Family ; Cyclone IV E ; |
||||
; Device ; EP4CE10E22C8 ; |
||||
; Timing Models ; Final ; |
||||
; Total logic elements ; 16 / 10,320 ( < 1 % ) ; |
||||
; Total combinational functions ; 15 / 10,320 ( < 1 % ) ; |
||||
; Dedicated logic registers ; 5 / 10,320 ( < 1 % ) ; |
||||
; Total registers ; 5 ; |
||||
; Total pins ; 17 / 92 ( 18 % ) ; |
||||
; Total virtual pins ; 0 ; |
||||
; Total memory bits ; 0 / 423,936 ( 0 % ) ; |
||||
; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; |
||||
; Total PLLs ; 0 / 2 ( 0 % ) ; |
||||
+------------------------------------+---------------------------------------------+ |
||||
|
||||
|
||||
+-----------------------------------------+ |
||||
; Flow Settings ; |
||||
+-------------------+---------------------+ |
||||
; Option ; Setting ; |
||||
+-------------------+---------------------+ |
||||
; Start date & time ; 04/24/2021 03:42:07 ; |
||||
; Main task ; Compilation ; |
||||
; Revision Name ; template ; |
||||
+-------------------+---------------------+ |
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------+ |
||||
; Flow Non-Default Global Settings ; |
||||
+-------------------------------------+----------------------------------------+---------------+-------------+------------+ |
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; |
||||
+-------------------------------------+----------------------------------------+---------------+-------------+------------+ |
||||
; COMPILER_SIGNATURE_ID ; 79871138160810.161922492745108 ; -- ; -- ; -- ; |
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; |
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; |
||||
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; |
||||
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; |
||||
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; |
||||
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; |
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; |
||||
+-------------------------------------+----------------------------------------+---------------+-------------+------------+ |
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------+ |
||||
; Flow Elapsed Time ; |
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ |
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; |
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ |
||||
; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 408 MB ; 00:00:23 ; |
||||
; Fitter ; 00:00:04 ; 1.0 ; 942 MB ; 00:00:04 ; |
||||
; Assembler ; 00:00:00 ; 1.0 ; 351 MB ; 00:00:01 ; |
||||
; Timing Analyzer ; 00:00:01 ; 1.0 ; 444 MB ; 00:00:01 ; |
||||
; Total ; 00:00:13 ; -- ; -- ; 00:00:29 ; |
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ |
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+ |
||||
; Flow OS Summary ; |
||||
+----------------------+------------------+----------------+------------+----------------+ |
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; |
||||
+----------------------+------------------+----------------+------------+----------------+ |
||||
; Analysis & Synthesis ; AW17R3 ; Ubuntu 20.04.2 ; 20 ; x86_64 ; |
||||
; Fitter ; AW17R3 ; Ubuntu 20.04.2 ; 20 ; x86_64 ; |
||||
; Assembler ; AW17R3 ; Ubuntu 20.04.2 ; 20 ; x86_64 ; |
||||
; Timing Analyzer ; AW17R3 ; Ubuntu 20.04.2 ; 20 ; x86_64 ; |
||||
+----------------------+------------------+----------------+------------+----------------+ |
||||
|
||||
|
||||
------------ |
||||
; Flow Log ; |
||||
------------ |
||||
quartus_map --read_settings_files=on --write_settings_files=off template -c template |
||||
quartus_fit --read_settings_files=off --write_settings_files=off template -c template |
||||
quartus_asm --read_settings_files=off --write_settings_files=off template -c template |
||||
quartus_sta template -c template |
||||
|
||||
|
||||
|
||||
@ -0,0 +1,8 @@ |
||||
<sld_project_info> |
||||
<project> |
||||
<hash md5_digest_80b="46eabb10af4d2e3a4a38"/> |
||||
</project> |
||||
<file_info> |
||||
<file device="EP4CE10E22C8" path="template.sof" usercode="0xFFFFFFFF"/> |
||||
</file_info> |
||||
</sld_project_info> |
||||
@ -0,0 +1,14 @@ |
||||
Analysis & Synthesis Status : Successful - Sat Apr 24 03:42:16 2021 |
||||
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
Revision Name : template |
||||
Top-level Entity Name : template |
||||
Family : Cyclone IV E |
||||
Total logic elements : 16 |
||||
Total combinational functions : 15 |
||||
Dedicated logic registers : 5 |
||||
Total registers : 5 |
||||
Total pins : 17 |
||||
Total virtual pins : 0 |
||||
Total memory bits : 0 |
||||
Embedded Multiplier 9-bit elements : 0 |
||||
Total PLLs : 0 |
||||
@ -0,0 +1,216 @@ |
||||
-- Copyright (C) 2020 Intel Corporation. All rights reserved. |
||||
-- Your use of Intel Corporation's design tools, logic functions |
||||
-- and other software and tools, and any partner logic |
||||
-- functions, and any output files from any of the foregoing |
||||
-- (including device programming or simulation files), and any |
||||
-- associated documentation or information are expressly subject |
||||
-- to the terms and conditions of the Intel Program License |
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement, |
||||
-- the Intel FPGA IP License Agreement, or other applicable license |
||||
-- agreement, including, without limitation, that your use is for |
||||
-- the sole purpose of programming logic devices manufactured by |
||||
-- Intel and sold by Intel or its authorized distributors. Please |
||||
-- refer to the applicable agreement for further details, at |
||||
-- https://fpgasoftware.intel.com/eula. |
||||
-- |
||||
-- This is a Quartus Prime output file. It is for reporting purposes only, and is |
||||
-- not intended for use as a Quartus Prime input file. This file cannot be used |
||||
-- to make Quartus Prime pin assignments - for instructions on how to make pin |
||||
-- assignments, please see Quartus Prime help. |
||||
--------------------------------------------------------------------------------- |
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------- |
||||
-- NC : No Connect. This pin has no internal connection to the device. |
||||
-- DNU : Do Not Use. This pin MUST NOT be connected. |
||||
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). |
||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC |
||||
-- of its bank. |
||||
-- Bank 1: 2.5V |
||||
-- Bank 2: 2.5V |
||||
-- Bank 3: 2.5V |
||||
-- Bank 4: 2.5V |
||||
-- Bank 5: 2.5V |
||||
-- Bank 6: 2.5V |
||||
-- Bank 7: 2.5V |
||||
-- Bank 8: 2.5V |
||||
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. |
||||
-- It can also be used to report unused dedicated pins. The connection |
||||
-- on the board for unused dedicated pins depends on whether this will |
||||
-- be used in a future design. One example is device migration. When |
||||
-- using device migration, refer to the device pin-tables. If it is a |
||||
-- GND pin in the pin table or if it will not be used in a future design |
||||
-- for another purpose the it MUST be connected to GND. If it is an unused |
||||
-- dedicated pin, then it can be connected to a valid signal on the board |
||||
-- (low, high, or toggling) if that signal is required for a different |
||||
-- revision of the design. |
||||
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. |
||||
-- This pin should be connected to GND. It may also be connected to a |
||||
-- valid signal on the board (low, high, or toggling) if that signal |
||||
-- is required for a different revision of the design. |
||||
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND |
||||
-- or leave it unconnected. |
||||
-- RESERVED : Unused I/O pin, which MUST be left unconnected. |
||||
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. |
||||
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. |
||||
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. |
||||
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. |
||||
--------------------------------------------------------------------------------- |
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------- |
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode. |
||||
--------------------------------------------------------------------------------- |
||||
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
CHIP "template" ASSIGNED TO AN: EP4CE10E22C8 |
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment |
||||
------------------------------------------------------------------------------------------------------------- |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : : : : 1 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : : : : 1 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 3 : : : : 1 : |
||||
GND : 4 : gnd : : : : |
||||
VCCINT : 5 : power : : 1.2V : : |
||||
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : input : 2.5 V : : 1 : N |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 7 : : : : 1 : |
||||
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : input : 2.5 V : : 1 : N |
||||
nSTATUS : 9 : : : : 1 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 10 : : : : 1 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 : |
||||
~ALTERA_DCLK~ : 12 : output : 2.5 V : : 1 : N |
||||
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 13 : input : 2.5 V : : 1 : N |
||||
nCONFIG : 14 : : : : 1 : |
||||
TDI : 15 : input : : : 1 : |
||||
TCK : 16 : input : : : 1 : |
||||
VCCIO1 : 17 : power : : 2.5V : 1 : |
||||
TMS : 18 : input : : : 1 : |
||||
GND : 19 : gnd : : : : |
||||
TDO : 20 : output : : : 1 : |
||||
nCE : 21 : : : : 1 : |
||||
GND : 22 : gnd : : : : |
||||
GND+ : 23 : : : : 1 : |
||||
GND+ : 24 : : : : 2 : |
||||
GND+ : 25 : : : : 2 : |
||||
VCCIO2 : 26 : power : : 2.5V : 2 : |
||||
GND : 27 : gnd : : : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 28 : : : : 2 : |
||||
VCCINT : 29 : power : : 1.2V : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 30 : : : : 2 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 31 : : : : 2 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 32 : : : : 2 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 33 : : : : 2 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 34 : : : : 2 : |
||||
VCCA1 : 35 : power : : 2.5V : : |
||||
GNDA1 : 36 : gnd : : : : |
||||
VCCD_PLL1 : 37 : power : : 1.2V : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 38 : : : : 3 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 : |
||||
VCCIO3 : 40 : power : : 2.5V : 3 : |
||||
GND : 41 : gnd : : : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 : |
||||
VCCINT : 45 : power : : 1.2V : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 3 : |
||||
VCCIO3 : 47 : power : : 2.5V : 3 : |
||||
GND : 48 : gnd : : : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 52 : : : : 3 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 53 : : : : 3 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 54 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 55 : : : : 4 : |
||||
VCCIO4 : 56 : power : : 2.5V : 4 : |
||||
GND : 57 : gnd : : : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 : |
||||
VCCINT : 61 : power : : 1.2V : : |
||||
VCCIO4 : 62 : power : : 2.5V : 4 : |
||||
GND : 63 : gnd : : : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 65 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 66 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 70 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 73 : : : : 5 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 74 : : : : 5 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 75 : : : : 5 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 5 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 77 : : : : 5 : |
||||
VCCINT : 78 : power : : 1.2V : : |
||||
GND : 79 : gnd : : : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 80 : : : : 5 : |
||||
VCCIO5 : 81 : power : : 2.5V : 5 : |
||||
GND : 82 : gnd : : : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 5 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 84 : : : : 5 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 85 : : : : 5 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 86 : : : : 5 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 5 : |
||||
GND+ : 88 : : : : 5 : |
||||
GND+ : 89 : : : : 5 : |
||||
K[2] : 90 : input : 2.5 V : : 6 : Y |
||||
K[3] : 91 : input : 2.5 V : : 6 : Y |
||||
CONF_DONE : 92 : : : : 6 : |
||||
VCCIO6 : 93 : power : : 2.5V : 6 : |
||||
MSEL0 : 94 : : : : 6 : |
||||
GND : 95 : gnd : : : : |
||||
MSEL1 : 96 : : : : 6 : |
||||
MSEL2 : 97 : : : : 6 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 : |
||||
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 101 : output : 2.5 V : : 6 : N |
||||
VCCINT : 102 : power : : 1.2V : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 105 : : : : 6 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 106 : : : : 6 : |
||||
VCCA2 : 107 : power : : 2.5V : : |
||||
GNDA2 : 108 : gnd : : : : |
||||
VCCD_PLL2 : 109 : power : : 1.2V : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 110 : : : : 7 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 111 : : : : 7 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 112 : : : : 7 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 113 : : : : 7 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 114 : : : : 7 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 115 : : : : 7 : |
||||
VCCINT : 116 : power : : 1.2V : : |
||||
VCCIO7 : 117 : power : : 2.5V : 7 : |
||||
GND : 118 : gnd : : : : |
||||
SEG[6] : 119 : output : 2.5 V : : 7 : Y |
||||
SEG[5] : 120 : output : 2.5 V : : 7 : Y |
||||
SEG[4] : 121 : output : 2.5 V : : 7 : Y |
||||
VCCIO7 : 122 : power : : 2.5V : 7 : |
||||
GND : 123 : gnd : : : : |
||||
SEG[3] : 124 : output : 2.5 V : : 7 : Y |
||||
SEG[2] : 125 : output : 2.5 V : : 7 : Y |
||||
SEG[1] : 126 : output : 2.5 V : : 7 : Y |
||||
SEG[0] : 127 : output : 2.5 V : : 7 : Y |
||||
HEX[0] : 128 : output : 2.5 V : : 8 : Y |
||||
HEX[1] : 129 : output : 2.5 V : : 8 : Y |
||||
VCCIO8 : 130 : power : : 2.5V : 8 : |
||||
GND : 131 : gnd : : : : |
||||
HEX[2] : 132 : output : 2.5 V : : 8 : Y |
||||
HEX[3] : 133 : output : 2.5 V : : 8 : Y |
||||
VCCINT : 134 : power : : 1.2V : : |
||||
HEX[4] : 135 : output : 2.5 V : : 8 : Y |
||||
HEX[5] : 136 : output : 2.5 V : : 8 : Y |
||||
HEX[6] : 137 : output : 2.5 V : : 8 : Y |
||||
HEX[7] : 138 : output : 2.5 V : : 8 : Y |
||||
VCCIO8 : 139 : power : : 2.5V : 8 : |
||||
GND : 140 : gnd : : : : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 141 : : : : 8 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 142 : : : : 8 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 143 : : : : 8 : |
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : 144 : : : : 8 : |
||||
GND : EPAD : : : : : |
||||
@ -0,0 +1 @@ |
||||
<sld_project_info/> |
||||
Binary file not shown.
@ -0,0 +1,707 @@ |
||||
Timing Analyzer report for template |
||||
Sat Apr 24 03:42:23 2021 |
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
|
||||
|
||||
--------------------- |
||||
; Table of Contents ; |
||||
--------------------- |
||||
1. Legal Notice |
||||
2. Timing Analyzer Summary |
||||
3. Parallel Compilation |
||||
4. Clocks |
||||
5. Slow 1200mV 85C Model Fmax Summary |
||||
6. Timing Closure Recommendations |
||||
7. Slow 1200mV 85C Model Setup Summary |
||||
8. Slow 1200mV 85C Model Hold Summary |
||||
9. Slow 1200mV 85C Model Recovery Summary |
||||
10. Slow 1200mV 85C Model Removal Summary |
||||
11. Slow 1200mV 85C Model Minimum Pulse Width Summary |
||||
12. Slow 1200mV 85C Model Setup: 'K[2]' |
||||
13. Slow 1200mV 85C Model Hold: 'K[2]' |
||||
14. Slow 1200mV 85C Model Metastability Summary |
||||
15. Slow 1200mV 0C Model Fmax Summary |
||||
16. Slow 1200mV 0C Model Setup Summary |
||||
17. Slow 1200mV 0C Model Hold Summary |
||||
18. Slow 1200mV 0C Model Recovery Summary |
||||
19. Slow 1200mV 0C Model Removal Summary |
||||
20. Slow 1200mV 0C Model Minimum Pulse Width Summary |
||||
21. Slow 1200mV 0C Model Setup: 'K[2]' |
||||
22. Slow 1200mV 0C Model Hold: 'K[2]' |
||||
23. Slow 1200mV 0C Model Metastability Summary |
||||
24. Fast 1200mV 0C Model Setup Summary |
||||
25. Fast 1200mV 0C Model Hold Summary |
||||
26. Fast 1200mV 0C Model Recovery Summary |
||||
27. Fast 1200mV 0C Model Removal Summary |
||||
28. Fast 1200mV 0C Model Minimum Pulse Width Summary |
||||
29. Fast 1200mV 0C Model Setup: 'K[2]' |
||||
30. Fast 1200mV 0C Model Hold: 'K[2]' |
||||
31. Fast 1200mV 0C Model Metastability Summary |
||||
32. Multicorner Timing Analysis Summary |
||||
33. Board Trace Model Assignments |
||||
34. Input Transition Times |
||||
35. Signal Integrity Metrics (Slow 1200mv 0c Model) |
||||
36. Signal Integrity Metrics (Slow 1200mv 85c Model) |
||||
37. Signal Integrity Metrics (Fast 1200mv 0c Model) |
||||
38. Setup Transfers |
||||
39. Hold Transfers |
||||
40. Report TCCS |
||||
41. Report RSKM |
||||
42. Unconstrained Paths Summary |
||||
43. Clock Status Summary |
||||
44. Unconstrained Input Ports |
||||
45. Unconstrained Output Ports |
||||
46. Unconstrained Input Ports |
||||
47. Unconstrained Output Ports |
||||
48. Timing Analyzer Messages |
||||
|
||||
|
||||
|
||||
---------------- |
||||
; Legal Notice ; |
||||
---------------- |
||||
Copyright (C) 2020 Intel Corporation. All rights reserved. |
||||
Your use of Intel Corporation's design tools, logic functions |
||||
and other software and tools, and any partner logic |
||||
functions, and any output files from any of the foregoing |
||||
(including device programming or simulation files), and any |
||||
associated documentation or information are expressly subject |
||||
to the terms and conditions of the Intel Program License |
||||
Subscription Agreement, the Intel Quartus Prime License Agreement, |
||||
the Intel FPGA IP License Agreement, or other applicable license |
||||
agreement, including, without limitation, that your use is for |
||||
the sole purpose of programming logic devices manufactured by |
||||
Intel and sold by Intel or its authorized distributors. Please |
||||
refer to the applicable agreement for further details, at |
||||
https://fpgasoftware.intel.com/eula. |
||||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+ |
||||
; Timing Analyzer Summary ; |
||||
+-----------------------+-----------------------------------------------------+ |
||||
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; |
||||
; Timing Analyzer ; Legacy Timing Analyzer ; |
||||
; Revision Name ; template ; |
||||
; Device Family ; Cyclone IV E ; |
||||
; Device Name ; EP4CE10E22C8 ; |
||||
; Timing Models ; Final ; |
||||
; Delay Model ; Combined ; |
||||
; Rise/Fall Delays ; Enabled ; |
||||
+-----------------------+-----------------------------------------------------+ |
||||
|
||||
|
||||
+------------------------------------------+ |
||||
; Parallel Compilation ; |
||||
+----------------------------+-------------+ |
||||
; Processors ; Number ; |
||||
+----------------------------+-------------+ |
||||
; Number detected on machine ; 8 ; |
||||
; Maximum allowed ; 4 ; |
||||
; ; ; |
||||
; Average used ; 1.01 ; |
||||
; Maximum used ; 4 ; |
||||
; ; ; |
||||
; Usage by Processor ; % Time Used ; |
||||
; Processor 1 ; 100.0% ; |
||||
; Processor 2 ; 0.3% ; |
||||
; Processors 3-4 ; 0.2% ; |
||||
+----------------------------+-------------+ |
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Clocks ; |
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ |
||||
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; |
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ |
||||
; K[2] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { K[2] } ; |
||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ |
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------+ |
||||
; Slow 1200mV 85C Model Fmax Summary ; |
||||
+------------+-----------------+------------+---------------------------------------------------------------+ |
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ; |
||||
+------------+-----------------+------------+---------------------------------------------------------------+ |
||||
; 737.46 MHz ; 250.0 MHz ; K[2] ; limit due to minimum period restriction (max I/O toggle rate) ; |
||||
+------------+-----------------+------------+---------------------------------------------------------------+ |
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. |
||||
|
||||
|
||||
---------------------------------- |
||||
; Timing Closure Recommendations ; |
||||
---------------------------------- |
||||
HTML report is unavailable in plain text report export. |
||||
|
||||
|
||||
+-------------------------------------+ |
||||
; Slow 1200mV 85C Model Setup Summary ; |
||||
+-------+--------+--------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+--------+--------------------+ |
||||
; K[2] ; -0.356 ; -0.706 ; |
||||
+-------+--------+--------------------+ |
||||
|
||||
|
||||
+------------------------------------+ |
||||
; Slow 1200mV 85C Model Hold Summary ; |
||||
+-------+-------+--------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+-------+--------------------+ |
||||
; K[2] ; 0.453 ; 0.000 ; |
||||
+-------+-------+--------------------+ |
||||
|
||||
|
||||
------------------------------------------ |
||||
; Slow 1200mV 85C Model Recovery Summary ; |
||||
------------------------------------------ |
||||
No paths to report. |
||||
|
||||
|
||||
----------------------------------------- |
||||
; Slow 1200mV 85C Model Removal Summary ; |
||||
----------------------------------------- |
||||
No paths to report. |
||||
|
||||
|
||||
+---------------------------------------------------+ |
||||
; Slow 1200mV 85C Model Minimum Pulse Width Summary ; |
||||
+-------+--------+----------------------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+--------+----------------------------------+ |
||||
; K[2] ; -3.000 ; -10.435 ; |
||||
+-------+--------+----------------------------------+ |
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Slow 1200mV 85C Model Setup: 'K[2]' ; |
||||
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; |
||||
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; -0.356 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.276 ; |
||||
; -0.325 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.245 ; |
||||
; -0.324 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.244 ; |
||||
; -0.026 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.946 ; |
||||
; -0.026 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.946 ; |
||||
; -0.023 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.943 ; |
||||
; 0.062 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ; |
||||
; 0.062 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ; |
||||
; 0.062 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ; |
||||
; 0.098 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.822 ; |
||||
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Slow 1200mV 85C Model Hold: 'K[2]' ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; 0.453 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ; |
||||
; 0.453 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ; |
||||
; 0.453 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ; |
||||
; 0.465 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.758 ; |
||||
; 0.524 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.817 ; |
||||
; 0.527 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.820 ; |
||||
; 0.527 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.820 ; |
||||
; 0.772 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.065 ; |
||||
; 0.821 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.114 ; |
||||
; 0.840 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.133 ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
|
||||
|
||||
----------------------------------------------- |
||||
; Slow 1200mV 85C Model Metastability Summary ; |
||||
----------------------------------------------- |
||||
No synchronizer chains to report. |
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------+ |
||||
; Slow 1200mV 0C Model Fmax Summary ; |
||||
+------------+-----------------+------------+---------------------------------------------------------------+ |
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ; |
||||
+------------+-----------------+------------+---------------------------------------------------------------+ |
||||
; 820.34 MHz ; 250.0 MHz ; K[2] ; limit due to minimum period restriction (max I/O toggle rate) ; |
||||
+------------+-----------------+------------+---------------------------------------------------------------+ |
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. |
||||
|
||||
|
||||
+------------------------------------+ |
||||
; Slow 1200mV 0C Model Setup Summary ; |
||||
+-------+--------+-------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+--------+-------------------+ |
||||
; K[2] ; -0.219 ; -0.412 ; |
||||
+-------+--------+-------------------+ |
||||
|
||||
|
||||
+-----------------------------------+ |
||||
; Slow 1200mV 0C Model Hold Summary ; |
||||
+-------+-------+-------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+-------+-------------------+ |
||||
; K[2] ; 0.401 ; 0.000 ; |
||||
+-------+-------+-------------------+ |
||||
|
||||
|
||||
----------------------------------------- |
||||
; Slow 1200mV 0C Model Recovery Summary ; |
||||
----------------------------------------- |
||||
No paths to report. |
||||
|
||||
|
||||
---------------------------------------- |
||||
; Slow 1200mV 0C Model Removal Summary ; |
||||
---------------------------------------- |
||||
No paths to report. |
||||
|
||||
|
||||
+--------------------------------------------------+ |
||||
; Slow 1200mV 0C Model Minimum Pulse Width Summary ; |
||||
+-------+--------+---------------------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+--------+---------------------------------+ |
||||
; K[2] ; -3.000 ; -10.435 ; |
||||
+-------+--------+---------------------------------+ |
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Slow 1200mV 0C Model Setup: 'K[2]' ; |
||||
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; |
||||
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; -0.219 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.148 ; |
||||
; -0.194 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.123 ; |
||||
; -0.193 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.122 ; |
||||
; 0.070 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.859 ; |
||||
; 0.070 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.859 ; |
||||
; 0.073 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.856 ; |
||||
; 0.159 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ; |
||||
; 0.159 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ; |
||||
; 0.159 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ; |
||||
; 0.184 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.745 ; |
||||
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Slow 1200mV 0C Model Hold: 'K[2]' ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; 0.401 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ; |
||||
; 0.401 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ; |
||||
; 0.401 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ; |
||||
; 0.416 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.684 ; |
||||
; 0.482 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.750 ; |
||||
; 0.484 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.752 ; |
||||
; 0.484 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.752 ; |
||||
; 0.716 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.984 ; |
||||
; 0.762 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 1.030 ; |
||||
; 0.782 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 1.050 ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
|
||||
|
||||
---------------------------------------------- |
||||
; Slow 1200mV 0C Model Metastability Summary ; |
||||
---------------------------------------------- |
||||
No synchronizer chains to report. |
||||
|
||||
|
||||
+------------------------------------+ |
||||
; Fast 1200mV 0C Model Setup Summary ; |
||||
+-------+-------+--------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+-------+--------------------+ |
||||
; K[2] ; 0.404 ; 0.000 ; |
||||
+-------+-------+--------------------+ |
||||
|
||||
|
||||
+-----------------------------------+ |
||||
; Fast 1200mV 0C Model Hold Summary ; |
||||
+-------+-------+-------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+-------+-------------------+ |
||||
; K[2] ; 0.187 ; 0.000 ; |
||||
+-------+-------+-------------------+ |
||||
|
||||
|
||||
----------------------------------------- |
||||
; Fast 1200mV 0C Model Recovery Summary ; |
||||
----------------------------------------- |
||||
No paths to report. |
||||
|
||||
|
||||
---------------------------------------- |
||||
; Fast 1200mV 0C Model Removal Summary ; |
||||
---------------------------------------- |
||||
No paths to report. |
||||
|
||||
|
||||
+--------------------------------------------------+ |
||||
; Fast 1200mV 0C Model Minimum Pulse Width Summary ; |
||||
+-------+--------+---------------------------------+ |
||||
; Clock ; Slack ; End Point TNS ; |
||||
+-------+--------+---------------------------------+ |
||||
; K[2] ; -3.000 ; -8.315 ; |
||||
+-------+--------+---------------------------------+ |
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Fast 1200mV 0C Model Setup: 'K[2]' ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; 0.404 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.547 ; |
||||
; 0.420 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.531 ; |
||||
; 0.422 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.529 ; |
||||
; 0.552 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.399 ; |
||||
; 0.553 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.398 ; |
||||
; 0.560 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.391 ; |
||||
; 0.592 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ; |
||||
; 0.592 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ; |
||||
; 0.592 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ; |
||||
; 0.601 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.350 ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Fast 1200mV 0C Model Hold: 'K[2]' ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
; 0.187 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ; |
||||
; 0.187 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ; |
||||
; 0.187 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ; |
||||
; 0.194 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.314 ; |
||||
; 0.214 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.334 ; |
||||
; 0.215 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.335 ; |
||||
; 0.216 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.336 ; |
||||
; 0.310 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.430 ; |
||||
; 0.337 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.457 ; |
||||
; 0.348 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.468 ; |
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ |
||||
|
||||
|
||||
---------------------------------------------- |
||||
; Fast 1200mV 0C Model Metastability Summary ; |
||||
---------------------------------------------- |
||||
No synchronizer chains to report. |
||||
|
||||
|
||||
+------------------------------------------------------------------------------+ |
||||
; Multicorner Timing Analysis Summary ; |
||||
+------------------+--------+-------+----------+---------+---------------------+ |
||||
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; |
||||
+------------------+--------+-------+----------+---------+---------------------+ |
||||
; Worst-case Slack ; -0.356 ; 0.187 ; N/A ; N/A ; -3.000 ; |
||||
; K[2] ; -0.356 ; 0.187 ; N/A ; N/A ; -3.000 ; |
||||
; Design-wide TNS ; -0.706 ; 0.0 ; 0.0 ; 0.0 ; -10.435 ; |
||||
; K[2] ; -0.706 ; 0.000 ; N/A ; N/A ; -10.435 ; |
||||
+------------------+--------+-------+----------+---------+---------------------+ |
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Board Trace Model Assignments ; |
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ |
||||
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; |
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ |
||||
; HEX[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; HEX[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; HEX[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; HEX[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; HEX[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; HEX[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; HEX[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; HEX[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; SEG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; SEG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; SEG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; SEG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; SEG[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; SEG[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; SEG[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ |
||||
|
||||
|
||||
+----------------------------------------------------------------------------+ |
||||
; Input Transition Times ; |
||||
+-------------------------+--------------+-----------------+-----------------+ |
||||
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; |
||||
+-------------------------+--------------+-----------------+-----------------+ |
||||
; K[2] ; 2.5 V ; 2000 ps ; 2000 ps ; |
||||
; K[3] ; 2.5 V ; 2000 ps ; 2000 ps ; |
||||
; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; |
||||
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; |
||||
; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; |
||||
+-------------------------+--------------+-----------------+-----------------+ |
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Signal Integrity Metrics (Slow 1200mv 0c Model) ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; |
||||
; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; |
||||
; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; |
||||
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; |
||||
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Signal Integrity Metrics (Slow 1200mv 85c Model) ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; |
||||
; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; |
||||
; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; |
||||
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; |
||||
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
||||
; Signal Integrity Metrics (Fast 1200mv 0c Model) ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; |
||||
; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; |
||||
; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; |
||||
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; |
||||
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; |
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
||||
|
||||
|
||||
+-------------------------------------------------------------------+ |
||||
; Setup Transfers ; |
||||
+------------+----------+----------+----------+----------+----------+ |
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
||||
+------------+----------+----------+----------+----------+----------+ |
||||
; K[2] ; K[2] ; 10 ; 0 ; 0 ; 0 ; |
||||
+------------+----------+----------+----------+----------+----------+ |
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. |
||||
|
||||
|
||||
+-------------------------------------------------------------------+ |
||||
; Hold Transfers ; |
||||
+------------+----------+----------+----------+----------+----------+ |
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
||||
+------------+----------+----------+----------+----------+----------+ |
||||
; K[2] ; K[2] ; 10 ; 0 ; 0 ; 0 ; |
||||
+------------+----------+----------+----------+----------+----------+ |
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. |
||||
|
||||
|
||||
--------------- |
||||
; Report TCCS ; |
||||
--------------- |
||||
No dedicated SERDES Transmitter circuitry present in device or used in design |
||||
|
||||
|
||||
--------------- |
||||
; Report RSKM ; |
||||
--------------- |
||||
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design |
||||
|
||||
|
||||
+------------------------------------------------+ |
||||
; Unconstrained Paths Summary ; |
||||
+---------------------------------+-------+------+ |
||||
; Property ; Setup ; Hold ; |
||||
+---------------------------------+-------+------+ |
||||
; Illegal Clocks ; 0 ; 0 ; |
||||
; Unconstrained Clocks ; 0 ; 0 ; |
||||
; Unconstrained Input Ports ; 1 ; 1 ; |
||||
; Unconstrained Input Port Paths ; 1 ; 1 ; |
||||
; Unconstrained Output Ports ; 10 ; 10 ; |
||||
; Unconstrained Output Port Paths ; 41 ; 41 ; |
||||
+---------------------------------+-------+------+ |
||||
|
||||
|
||||
+-------------------------------------+ |
||||
; Clock Status Summary ; |
||||
+--------+-------+------+-------------+ |
||||
; Target ; Clock ; Type ; Status ; |
||||
+--------+-------+------+-------------+ |
||||
; K[2] ; K[2] ; Base ; Constrained ; |
||||
+--------+-------+------+-------------+ |
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+ |
||||
; Unconstrained Input Ports ; |
||||
+------------+--------------------------------------------------------------------------------------+ |
||||
; Input Port ; Comment ; |
||||
+------------+--------------------------------------------------------------------------------------+ |
||||
; K[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
+------------+--------------------------------------------------------------------------------------+ |
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------+ |
||||
; Unconstrained Output Ports ; |
||||
+-------------+---------------------------------------------------------------------------------------+ |
||||
; Output Port ; Comment ; |
||||
+-------------+---------------------------------------------------------------------------------------+ |
||||
; HEX[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; HEX[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; HEX[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
+-------------+---------------------------------------------------------------------------------------+ |
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+ |
||||
; Unconstrained Input Ports ; |
||||
+------------+--------------------------------------------------------------------------------------+ |
||||
; Input Port ; Comment ; |
||||
+------------+--------------------------------------------------------------------------------------+ |
||||
; K[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
+------------+--------------------------------------------------------------------------------------+ |
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------+ |
||||
; Unconstrained Output Ports ; |
||||
+-------------+---------------------------------------------------------------------------------------+ |
||||
; Output Port ; Comment ; |
||||
+-------------+---------------------------------------------------------------------------------------+ |
||||
; HEX[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; HEX[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; HEX[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
; SEG[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; |
||||
+-------------+---------------------------------------------------------------------------------------+ |
||||
|
||||
|
||||
+--------------------------+ |
||||
; Timing Analyzer Messages ; |
||||
+--------------------------+ |
||||
Info: ******************************************************************* |
||||
Info: Running Quartus Prime Timing Analyzer |
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition |
||||
Info: Processing started: Sat Apr 24 03:42:22 2021 |
||||
Info: Command: quartus_sta template -c template |
||||
Info: qsta_default_script.tcl version: #1 |
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. |
||||
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected |
||||
Info (21077): Low junction temperature is 0 degrees C |
||||
Info (21077): High junction temperature is 85 degrees C |
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. |
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" |
||||
Info (332105): Deriving Clocks |
||||
Info (332105): create_clock -period 1.000 -name K[2] K[2] |
||||
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" |
||||
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. |
||||
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON |
||||
Info: Analyzing Slow 1200mV 85C Model |
||||
Critical Warning (332148): Timing requirements not met |
||||
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. |
||||
Info (332146): Worst-case setup slack is -0.356 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): -0.356 -0.706 K[2] |
||||
Info (332146): Worst-case hold slack is 0.453 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): 0.453 0.000 K[2] |
||||
Info (332140): No Recovery paths to report |
||||
Info (332140): No Removal paths to report |
||||
Info (332146): Worst-case minimum pulse width slack is -3.000 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): -3.000 -10.435 K[2] |
||||
Info: Analyzing Slow 1200mV 0C Model |
||||
Info (334003): Started post-fitting delay annotation |
||||
Info (334004): Delay annotation completed successfully |
||||
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. |
||||
Critical Warning (332148): Timing requirements not met |
||||
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. |
||||
Info (332146): Worst-case setup slack is -0.219 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): -0.219 -0.412 K[2] |
||||
Info (332146): Worst-case hold slack is 0.401 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): 0.401 0.000 K[2] |
||||
Info (332140): No Recovery paths to report |
||||
Info (332140): No Removal paths to report |
||||
Info (332146): Worst-case minimum pulse width slack is -3.000 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): -3.000 -10.435 K[2] |
||||
Info: Analyzing Fast 1200mV 0C Model |
||||
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. |
||||
Info (332146): Worst-case setup slack is 0.404 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): 0.404 0.000 K[2] |
||||
Info (332146): Worst-case hold slack is 0.187 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): 0.187 0.000 K[2] |
||||
Info (332140): No Recovery paths to report |
||||
Info (332140): No Removal paths to report |
||||
Critical Warning (332148): Timing requirements not met |
||||
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. |
||||
Info (332146): Worst-case minimum pulse width slack is -3.000 |
||||
Info (332119): Slack End Point TNS Clock |
||||
Info (332119): ========= =================== ===================== |
||||
Info (332119): -3.000 -8.315 K[2] |
||||
Info (332102): Design is not fully constrained for setup requirements |
||||
Info (332102): Design is not fully constrained for hold requirements |
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings |
||||
Info: Peak virtual memory: 444 megabytes |
||||
Info: Processing ended: Sat Apr 24 03:42:23 2021 |
||||
Info: Elapsed time: 00:00:01 |
||||
Info: Total CPU time (on all processors): 00:00:01 |
||||
|
||||
|
||||
@ -0,0 +1,41 @@ |
||||
------------------------------------------------------------ |
||||
Timing Analyzer Summary |
||||
------------------------------------------------------------ |
||||
|
||||
Type : Slow 1200mV 85C Model Setup 'K[2]' |
||||
Slack : -0.356 |
||||
TNS : -0.706 |
||||
|
||||
Type : Slow 1200mV 85C Model Hold 'K[2]' |
||||
Slack : 0.453 |
||||
TNS : 0.000 |
||||
|
||||
Type : Slow 1200mV 85C Model Minimum Pulse Width 'K[2]' |
||||
Slack : -3.000 |
||||
TNS : -10.435 |
||||
|
||||
Type : Slow 1200mV 0C Model Setup 'K[2]' |
||||
Slack : -0.219 |
||||
TNS : -0.412 |
||||
|
||||
Type : Slow 1200mV 0C Model Hold 'K[2]' |
||||
Slack : 0.401 |
||||
TNS : 0.000 |
||||
|
||||
Type : Slow 1200mV 0C Model Minimum Pulse Width 'K[2]' |
||||
Slack : -3.000 |
||||
TNS : -10.435 |
||||
|
||||
Type : Fast 1200mV 0C Model Setup 'K[2]' |
||||
Slack : 0.404 |
||||
TNS : 0.000 |
||||
|
||||
Type : Fast 1200mV 0C Model Hold 'K[2]' |
||||
Slack : 0.187 |
||||
TNS : 0.000 |
||||
|
||||
Type : Fast 1200mV 0C Model Minimum Pulse Width 'K[2]' |
||||
Slack : -3.000 |
||||
TNS : -8.315 |
||||
|
||||
------------------------------------------------------------ |
||||
@ -0,0 +1,163 @@ |
||||
/* |
||||
WARNING: Do NOT edit the input and output ports in this file in a text |
||||
editor if you plan to continue editing the block that represents it in |
||||
the Block Editor! File corruption is VERY likely to occur. |
||||
*/ |
||||
/* |
||||
Copyright (C) 2020 Intel Corporation. All rights reserved. |
||||
Your use of Intel Corporation's design tools, logic functions |
||||
and other software and tools, and any partner logic |
||||
functions, and any output files from any of the foregoing |
||||
(including device programming or simulation files), and any |
||||
associated documentation or information are expressly subject |
||||
to the terms and conditions of the Intel Program License |
||||
Subscription Agreement, the Intel Quartus Prime License Agreement, |
||||
the Intel FPGA IP License Agreement, or other applicable license |
||||
agreement, including, without limitation, that your use is for |
||||
the sole purpose of programming logic devices manufactured by |
||||
Intel and sold by Intel or its authorized distributors. Please |
||||
refer to the applicable agreement for further details, at |
||||
https://fpgasoftware.intel.com/eula. |
||||
*/ |
||||
(header "graphic" (version "1.4")) |
||||
(pin |
||||
(input) |
||||
(rect 136 296 304 312) |
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) |
||||
(text "K[2]" (rect 5 0 25 11)(font "Arial" )) |
||||
(pt 168 8) |
||||
(drawing |
||||
(line (pt 84 12)(pt 109 12)) |
||||
(line (pt 84 4)(pt 109 4)) |
||||
(line (pt 113 8)(pt 168 8)) |
||||
(line (pt 84 12)(pt 84 4)) |
||||
(line (pt 109 4)(pt 113 8)) |
||||
(line (pt 109 12)(pt 113 8)) |
||||
) |
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) |
||||
(annotation_block (location)(rect 80 312 136 328)) |
||||
) |
||||
(pin |
||||
(input) |
||||
(rect -104 224 64 240) |
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) |
||||
(text "K[3]" (rect 5 0 28 13)(font "Intel Clear" )) |
||||
(pt 168 8) |
||||
(drawing |
||||
(line (pt 84 12)(pt 109 12)) |
||||
(line (pt 84 4)(pt 109 4)) |
||||
(line (pt 113 8)(pt 168 8)) |
||||
(line (pt 84 12)(pt 84 4)) |
||||
(line (pt 109 4)(pt 113 8)) |
||||
(line (pt 109 12)(pt 113 8)) |
||||
) |
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) |
||||
(annotation_block (location)(rect -8 264 48 280)) |
||||
) |
||||
(pin |
||||
(output) |
||||
(rect 496 280 672 296) |
||||
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) |
||||
(text "HEX[0..7]" (rect 90 0 138 13)(font "Intel Clear" )) |
||||
(pt 0 8) |
||||
(drawing |
||||
(line (pt 0 8)(pt 52 8)) |
||||
(line (pt 52 4)(pt 78 4)) |
||||
(line (pt 52 12)(pt 78 12)) |
||||
(line (pt 52 12)(pt 52 4)) |
||||
(line (pt 78 4)(pt 82 8)) |
||||
(line (pt 82 8)(pt 78 12)) |
||||
(line (pt 78 12)(pt 82 8)) |
||||
) |
||||
(annotation_block (location)(rect 616 248 672 264)) |
||||
) |
||||
(pin |
||||
(output) |
||||
(rect 496 296 672 312) |
||||
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) |
||||
(text "SEG[0..6]" (rect 90 0 138 11)(font "Arial" )) |
||||
(pt 0 8) |
||||
(drawing |
||||
(line (pt 0 8)(pt 52 8)) |
||||
(line (pt 52 4)(pt 78 4)) |
||||
(line (pt 52 12)(pt 78 12)) |
||||
(line (pt 52 12)(pt 52 4)) |
||||
(line (pt 78 4)(pt 82 8)) |
||||
(line (pt 82 8)(pt 78 12)) |
||||
(line (pt 78 12)(pt 82 8)) |
||||
) |
||||
(annotation_block (location)(rect 672 312 736 328)) |
||||
) |
||||
(symbol |
||||
(rect 304 256 496 336) |
||||
(text "LED_7seg_driver" (rect 5 0 92 11)(font "Arial" )) |
||||
(text "inst" (rect 8 64 26 75)(font "Arial" )) |
||||
(port |
||||
(pt 0 32) |
||||
(input) |
||||
(text "D[0..7][0..4]" (rect 0 0 57 11)(font "Arial" )) |
||||
(text "D[0..7][0..4]" (rect 21 27 78 38)(font "Arial" )) |
||||
(line (pt 0 32)(pt 16 32)(line_width 3)) |
||||
) |
||||
(port |
||||
(pt 0 48) |
||||
(input) |
||||
(text "clk" (rect 0 0 15 11)(font "Arial" )) |
||||
(text "clk" (rect 21 43 36 54)(font "Arial" )) |
||||
(line (pt 0 48)(pt 16 48)) |
||||
) |
||||
(port |
||||
(pt 192 32) |
||||
(output) |
||||
(text "dig[0..7]" (rect 0 0 40 11)(font "Arial" )) |
||||
(text "dig[0..7]" (rect 138 27 171 38)(font "Arial" )) |
||||
(line (pt 192 32)(pt 176 32)(line_width 3)) |
||||
) |
||||
(port |
||||
(pt 192 48) |
||||
(output) |
||||
(text "SEG[6..0]" (rect 0 0 48 11)(font "Arial" )) |
||||
(text "SEG[6..0]" (rect 131 43 171 54)(font "Arial" )) |
||||
(line (pt 192 48)(pt 176 48)(line_width 3)) |
||||
) |
||||
(drawing |
||||
(rectangle (rect 16 16 176 64)) |
||||
) |
||||
) |
||||
(symbol |
||||
(rect 64 200 248 280) |
||||
(text "test" (rect 5 0 23 11)(font "Arial" )) |
||||
(text "inst4" (rect 8 64 33 77)(font "Intel Clear" )) |
||||
(port |
||||
(pt 0 32) |
||||
(input) |
||||
(text "test" (rect 0 0 18 11)(font "Arial" )) |
||||
(text "test" (rect 21 27 39 38)(font "Arial" )) |
||||
(line (pt 0 32)(pt 16 32)) |
||||
) |
||||
(port |
||||
(pt 184 32) |
||||
(output) |
||||
(text "number[7..0][4..0]" (rect 0 0 86 11)(font "Arial" )) |
||||
(text "number[7..0][4..0]" (rect 91 27 177 38)(font "Arial" )) |
||||
(line (pt 184 32)(pt 168 32)(line_width 3)) |
||||
) |
||||
(drawing |
||||
(rectangle (rect 16 16 168 64)) |
||||
) |
||||
) |
||||
(connector |
||||
(pt 304 288) |
||||
(pt 280 288) |
||||
(bus) |
||||
) |
||||
(connector |
||||
(pt 280 288) |
||||
(pt 280 232) |
||||
(bus) |
||||
) |
||||
(connector |
||||
(pt 248 232) |
||||
(pt 280 232) |
||||
(bus) |
||||
) |
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue