subdesign 7seg_driver (D[3..0]: input = VCC; SEG[6..0]: output;)
begin

case d[] is
	when 0 => SEG[6..0] = b"0000001";
	when 1 => SEG[6..0] = b"1001111";
	when 2 => SEG[6..0] = b"0010010";
	when 3 => SEG[6..0] = b"0000110";
	when 4 => SEG[6..0] = b"1001100";
	when 5 => SEG[6..0] = b"0100100";
	when 6 => SEG[6..0] = b"0100000";
	when 7 => SEG[6..0] = b"0001111";
	when 8 => SEG[6..0] = b"0000000";
	when 9 => SEG[6..0] = b"0000100";
	when 10 => SEG[6..0] = b"0001000";
	when 11 => SEG[6..0] = b"1100000";
	when 12 => SEG[6..0] = b"0110001";
	when 13 => SEG[6..0] = b"1000010";
	when 14 => SEG[6..0] = b"0110000";
	when 15 => SEG[6..0] = b"0111000";
	when others => SEG[6..0] = VCC;
end case;
end;