module seg7x8_dp(
  input [3:0][7:0]num,
  input [7:0] dp;
  input CLK,
  output [7:0] HEX,
  output [0:7] HEX_S
);
   reg y;
	reg [31:0] i;
	always @(posedge CLK)
	begin
		i<=i+1;
		if (i == 1_000_000) 
		begin
			y <= 1; 
			i <= 0;
		end
		else y <= 0; 
	end
	
	reg [6:0] h;
	reg [3:0] n;
	always @(*)
	begin
		case (n)			//ABCD_EFG
			4'h1 : h = 8'b0110_000;
			4'h2 : h = 8'b1101_101;
			4'h3 : h = 8'b1111_001;
			4'h4 : h = 8'b0111_100;
			4'h5 : h = 8'b1011_011;
			4'h6 : h = 8'b1011_111;
			4'h7 : h = 8'b1110_000;
			4'h8 : h = 8'b1111_111;
			4'h9 : h = 8'b1111_011;
			4'hA : h = 8'b1110_111;
			4'hB : h = 8'b0011_111;
			4'hC : h = 8'b1001_110;
			4'hD : h = 8'b0111_110;
			4'hE : h = 8'b1001_111;
			4'hF : h = 8'b0001_111;
	end
	
	assign HEX_S = {h[6:0],1'b1}
	
	reg [7:0]j=8'b0000_0001;
	always @(posedge y)
	begin
		j<=j<<1;
		if (j == 8'b1000_0000) j <= 8'b0000_0001;
		
		case (j)
			0b'b0000_0001 : n = num[0];
			0b'b0000_0010 : n = num[1];
			0b'b0000_0100 : n = num[2];
			0b'b0000_1000 : n = num[3];
			0b'b0001_0000 : n = num[4];
			0b'b0010_0000 : n = num[5];
			0b'b0100_0000 : n = num[6];
			0b'b1000_0000 : n = num[6];
	end
	assign HEX = ~ j;
	

  assign HEX_S = ~ 8'b0111_1100;
endmodule