# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 20:32:51  October 18, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		template_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE10E22C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:51  OCTOBER 18, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_location_assignment PIN_128 -to HEX[0]
set_location_assignment PIN_129 -to HEX[1]
set_location_assignment PIN_132 -to HEX[2]
set_location_assignment PIN_133 -to HEX[3]
set_location_assignment PIN_135 -to HEX[4]
set_location_assignment PIN_136 -to HEX[5]
set_location_assignment PIN_137 -to HEX[6]
set_location_assignment PIN_138 -to HEX[7]
set_location_assignment PIN_72 -to D[3]
set_location_assignment PIN_73 -to D[4]
set_location_assignment PIN_74 -to D[5]
set_location_assignment PIN_80 -to D[6]
set_location_assignment PIN_83 -to D[7]
set_location_assignment PIN_84 -to D[8]
set_location_assignment PIN_77 -to D[9]
set_location_assignment PIN_76 -to D[10]
set_location_assignment PIN_75 -to D[11]
set_location_assignment PIN_71 -to D[12]
set_location_assignment PIN_70 -to D[13]
set_location_assignment PIN_69 -to D[14]
set_location_assignment PIN_58 -to SW[1]
set_location_assignment PIN_60 -to SW[3]
set_location_assignment PIN_64 -to SW[4]
set_location_assignment PIN_65 -to SW[5]
set_location_assignment PIN_66 -to SW[6]
set_location_assignment PIN_67 -to SW[7]
set_location_assignment PIN_59 -to SW[2]
set_location_assignment PIN_68 -to SW[8]
set_location_assignment PIN_90 -to K[2]
set_location_assignment PIN_91 -to K[3]
set_location_assignment PIN_87 -to K[4]
set_location_assignment PIN_86 -to K[5]
set_location_assignment PIN_141 -to BELL
set_location_assignment PIN_2 -to VGA_R
set_location_assignment PIN_1 -to VGA_G
set_location_assignment PIN_144 -to VGA_B
set_location_assignment PIN_143 -to VGA_VS
set_location_assignment PIN_142 -to VGA_HS
set_location_assignment PIN_3 -to MEM_SDA
set_location_assignment PIN_7 -to MEM_SCK
set_location_assignment PIN_10 -to PS_2_DATA
set_location_assignment PIN_11 -to PS_2_SCK
set_location_assignment PIN_23 -to CLK_50M
set_location_assignment PIN_24 -to CLK_USER
set_location_assignment PIN_114 -to UART_TX
set_location_assignment PIN_113 -to UART_RX
set_location_assignment PIN_101 -to LCD_D[0]
set_location_assignment PIN_103 -to LCD_D[1]
set_location_assignment PIN_104 -to LCD_D[2]
set_location_assignment PIN_105 -to LCD_D[3]
set_location_assignment PIN_106 -to LCD_D[4]
set_location_assignment PIN_110 -to LCD_D[5]
set_location_assignment PIN_111 -to LCD_D[6]
set_location_assignment PIN_112 -to LCD_D[7]
set_location_assignment PIN_85 -to LCD_RS
set_location_assignment PIN_99 -to LCD_WR
set_location_assignment PIN_100 -to LCD_EN
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_127 -to HEX_S[0]
set_location_assignment PIN_126 -to HEX_S[1]
set_location_assignment PIN_125 -to HEX_S[2]
set_location_assignment PIN_124 -to HEX_S[3]
set_location_assignment PIN_121 -to HEX_S[4]
set_location_assignment PIN_120 -to HEX_S[5]
set_location_assignment PIN_119 -to HEX_S[6]
set_location_assignment PIN_115 -to HEX_S[7]
set_global_assignment -name VERILOG_FILE output_files/seg7x8_dp.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top