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80 lines
1.5 KiB
80 lines
1.5 KiB
module seg7x8_dp(
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input [31:0]num,
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input [7:0] dp,
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input CLK,
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output [7:0] HEX,
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output [0:7] HEX_S
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);
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reg y;
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reg [31:0] i;
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always @(posedge CLK)
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begin
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i<=i+1;
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if (i == 10_000)
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begin
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y <= 1;
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i <= 0;
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end
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else y <= 0;
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end
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reg [6:0] h;
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reg [3:0] n;
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always @(*)
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begin
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case (n) //ABCD_EFG
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4'h0 : h = 7'b1111_110;
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4'h1 : h = 7'b0110_000;
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4'h2 : h = 7'b1101_101;
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4'h3 : h = 7'b1111_001;
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4'h4 : h = 7'b0110_011;
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4'h5 : h = 7'b1011_011;
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4'h6 : h = 7'b1011_111;
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4'h7 : h = 7'b1110_000;
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4'h8 : h = 7'b1111_111;
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4'h9 : h = 7'b1111_011;
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4'hA : h = 7'b1110_111;
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4'hB : h = 7'b0011_111;
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4'hC : h = 7'b1001_110;
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4'hD : h = 7'b0111_101;
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4'hE : h = 7'b1001_111;
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4'hF : h = 7'b1000_111;
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endcase
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end
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reg DP = 0;
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assign HEX_S = {~h[6:0],~DP};
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reg [7:0]j=8'b0000_0001;
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always @(posedge y)
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begin
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j<=j<<1;
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if (j == 8'b1000_0000) j <= 8'b0000_0001;
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case (j)
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8'b1000_0000 : n <= num[3:0];
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8'b0100_0000 : n <= num[31:28];
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8'b0010_0000 : n <= num[27:24];
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8'b0001_0000 : n <= num[23:20];
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8'b0000_1000 : n <= num[19:16];
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8'b0000_0100 : n <= num[15:12];
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8'b0000_0010 : n <= num[11:8];
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8'b0000_0001 : n <= num[7:4];
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endcase
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case (j)
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8'b1000_0000 : DP <= dp[0];
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8'b0100_0000 : DP <= dp[1];
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8'b0010_0000 : DP <= dp[2];
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8'b0001_0000 : DP <= dp[3];
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8'b0000_1000 : DP <= dp[4];
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8'b0000_0100 : DP <= dp[5];
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8'b0000_0010 : DP <= dp[6];
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8'b0000_0001 : DP <= dp[7];
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endcase
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end
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assign HEX = ~ j;
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endmodule |