You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
708 lines
95 KiB
708 lines
95 KiB
4 years ago
|
Timing Analyzer report for template
|
||
|
|
Sat Apr 24 03:42:23 2021
|
||
|
|
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||
|
|
|
||
|
|
|
||
|
|
---------------------
|
||
|
|
; Table of Contents ;
|
||
|
|
---------------------
|
||
|
|
1. Legal Notice
|
||
|
|
2. Timing Analyzer Summary
|
||
|
|
3. Parallel Compilation
|
||
|
|
4. Clocks
|
||
|
|
5. Slow 1200mV 85C Model Fmax Summary
|
||
|
|
6. Timing Closure Recommendations
|
||
|
|
7. Slow 1200mV 85C Model Setup Summary
|
||
|
|
8. Slow 1200mV 85C Model Hold Summary
|
||
|
|
9. Slow 1200mV 85C Model Recovery Summary
|
||
|
|
10. Slow 1200mV 85C Model Removal Summary
|
||
|
|
11. Slow 1200mV 85C Model Minimum Pulse Width Summary
|
||
|
|
12. Slow 1200mV 85C Model Setup: 'K[2]'
|
||
|
|
13. Slow 1200mV 85C Model Hold: 'K[2]'
|
||
|
|
14. Slow 1200mV 85C Model Metastability Summary
|
||
|
|
15. Slow 1200mV 0C Model Fmax Summary
|
||
|
|
16. Slow 1200mV 0C Model Setup Summary
|
||
|
|
17. Slow 1200mV 0C Model Hold Summary
|
||
|
|
18. Slow 1200mV 0C Model Recovery Summary
|
||
|
|
19. Slow 1200mV 0C Model Removal Summary
|
||
|
|
20. Slow 1200mV 0C Model Minimum Pulse Width Summary
|
||
|
|
21. Slow 1200mV 0C Model Setup: 'K[2]'
|
||
|
|
22. Slow 1200mV 0C Model Hold: 'K[2]'
|
||
|
|
23. Slow 1200mV 0C Model Metastability Summary
|
||
|
|
24. Fast 1200mV 0C Model Setup Summary
|
||
|
|
25. Fast 1200mV 0C Model Hold Summary
|
||
|
|
26. Fast 1200mV 0C Model Recovery Summary
|
||
|
|
27. Fast 1200mV 0C Model Removal Summary
|
||
|
|
28. Fast 1200mV 0C Model Minimum Pulse Width Summary
|
||
|
|
29. Fast 1200mV 0C Model Setup: 'K[2]'
|
||
|
|
30. Fast 1200mV 0C Model Hold: 'K[2]'
|
||
|
|
31. Fast 1200mV 0C Model Metastability Summary
|
||
|
|
32. Multicorner Timing Analysis Summary
|
||
|
|
33. Board Trace Model Assignments
|
||
|
|
34. Input Transition Times
|
||
|
|
35. Signal Integrity Metrics (Slow 1200mv 0c Model)
|
||
|
|
36. Signal Integrity Metrics (Slow 1200mv 85c Model)
|
||
|
|
37. Signal Integrity Metrics (Fast 1200mv 0c Model)
|
||
|
|
38. Setup Transfers
|
||
|
|
39. Hold Transfers
|
||
|
|
40. Report TCCS
|
||
|
|
41. Report RSKM
|
||
|
|
42. Unconstrained Paths Summary
|
||
|
|
43. Clock Status Summary
|
||
|
|
44. Unconstrained Input Ports
|
||
|
|
45. Unconstrained Output Ports
|
||
|
|
46. Unconstrained Input Ports
|
||
|
|
47. Unconstrained Output Ports
|
||
|
|
48. Timing Analyzer Messages
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
----------------
|
||
|
|
; Legal Notice ;
|
||
|
|
----------------
|
||
|
|
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||
|
|
Your use of Intel Corporation's design tools, logic functions
|
||
|
|
and other software and tools, and any partner logic
|
||
|
|
functions, and any output files from any of the foregoing
|
||
|
|
(including device programming or simulation files), and any
|
||
|
|
associated documentation or information are expressly subject
|
||
|
|
to the terms and conditions of the Intel Program License
|
||
|
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
|
the Intel FPGA IP License Agreement, or other applicable license
|
||
|
|
agreement, including, without limitation, that your use is for
|
||
|
|
the sole purpose of programming logic devices manufactured by
|
||
|
|
Intel and sold by Intel or its authorized distributors. Please
|
||
|
|
refer to the applicable agreement for further details, at
|
||
|
|
https://fpgasoftware.intel.com/eula.
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------+
|
||
|
|
; Timing Analyzer Summary ;
|
||
|
|
+-----------------------+-----------------------------------------------------+
|
||
|
|
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||
|
|
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||
|
|
; Revision Name ; template ;
|
||
|
|
; Device Family ; Cyclone IV E ;
|
||
|
|
; Device Name ; EP4CE10E22C8 ;
|
||
|
|
; Timing Models ; Final ;
|
||
|
|
; Delay Model ; Combined ;
|
||
|
|
; Rise/Fall Delays ; Enabled ;
|
||
|
|
+-----------------------+-----------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------+
|
||
|
|
; Parallel Compilation ;
|
||
|
|
+----------------------------+-------------+
|
||
|
|
; Processors ; Number ;
|
||
|
|
+----------------------------+-------------+
|
||
|
|
; Number detected on machine ; 8 ;
|
||
|
|
; Maximum allowed ; 4 ;
|
||
|
|
; ; ;
|
||
|
|
; Average used ; 1.01 ;
|
||
|
|
; Maximum used ; 4 ;
|
||
|
|
; ; ;
|
||
|
|
; Usage by Processor ; % Time Used ;
|
||
|
|
; Processor 1 ; 100.0% ;
|
||
|
|
; Processor 2 ; 0.3% ;
|
||
|
|
; Processors 3-4 ; 0.2% ;
|
||
|
|
+----------------------------+-------------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Clocks ;
|
||
|
|
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
|
||
|
|
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
||
|
|
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
|
||
|
|
; K[2] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { K[2] } ;
|
||
|
|
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Fmax Summary ;
|
||
|
|
+------------+-----------------+------------+---------------------------------------------------------------+
|
||
|
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||
|
|
+------------+-----------------+------------+---------------------------------------------------------------+
|
||
|
|
; 737.46 MHz ; 250.0 MHz ; K[2] ; limit due to minimum period restriction (max I/O toggle rate) ;
|
||
|
|
+------------+-----------------+------------+---------------------------------------------------------------+
|
||
|
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------
|
||
|
|
; Timing Closure Recommendations ;
|
||
|
|
----------------------------------
|
||
|
|
HTML report is unavailable in plain text report export.
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Setup Summary ;
|
||
|
|
+-------+--------+--------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+--------+--------------------+
|
||
|
|
; K[2] ; -0.356 ; -0.706 ;
|
||
|
|
+-------+--------+--------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Hold Summary ;
|
||
|
|
+-------+-------+--------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+-------+--------------------+
|
||
|
|
; K[2] ; 0.453 ; 0.000 ;
|
||
|
|
+-------+-------+--------------------+
|
||
|
|
|
||
|
|
|
||
|
|
------------------------------------------
|
||
|
|
; Slow 1200mV 85C Model Recovery Summary ;
|
||
|
|
------------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
-----------------------------------------
|
||
|
|
; Slow 1200mV 85C Model Removal Summary ;
|
||
|
|
-----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
|
||
|
|
+-------+--------+----------------------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+--------+----------------------------------+
|
||
|
|
; K[2] ; -3.000 ; -10.435 ;
|
||
|
|
+-------+--------+----------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Setup: 'K[2]' ;
|
||
|
|
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; -0.356 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.276 ;
|
||
|
|
; -0.325 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.245 ;
|
||
|
|
; -0.324 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 1.244 ;
|
||
|
|
; -0.026 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.946 ;
|
||
|
|
; -0.026 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.946 ;
|
||
|
|
; -0.023 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.943 ;
|
||
|
|
; 0.062 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ;
|
||
|
|
; 0.062 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ;
|
||
|
|
; 0.062 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.858 ;
|
||
|
|
; 0.098 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.081 ; 0.822 ;
|
||
|
|
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 85C Model Hold: 'K[2]' ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; 0.453 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ;
|
||
|
|
; 0.453 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ;
|
||
|
|
; 0.453 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.746 ;
|
||
|
|
; 0.465 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.758 ;
|
||
|
|
; 0.524 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.817 ;
|
||
|
|
; 0.527 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.820 ;
|
||
|
|
; 0.527 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 0.820 ;
|
||
|
|
; 0.772 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.065 ;
|
||
|
|
; 0.821 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.114 ;
|
||
|
|
; 0.840 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.081 ; 1.133 ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
-----------------------------------------------
|
||
|
|
; Slow 1200mV 85C Model Metastability Summary ;
|
||
|
|
-----------------------------------------------
|
||
|
|
No synchronizer chains to report.
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Fmax Summary ;
|
||
|
|
+------------+-----------------+------------+---------------------------------------------------------------+
|
||
|
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||
|
|
+------------+-----------------+------------+---------------------------------------------------------------+
|
||
|
|
; 820.34 MHz ; 250.0 MHz ; K[2] ; limit due to minimum period restriction (max I/O toggle rate) ;
|
||
|
|
+------------+-----------------+------------+---------------------------------------------------------------+
|
||
|
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Setup Summary ;
|
||
|
|
+-------+--------+-------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+--------+-------------------+
|
||
|
|
; K[2] ; -0.219 ; -0.412 ;
|
||
|
|
+-------+--------+-------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Hold Summary ;
|
||
|
|
+-------+-------+-------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+-------+-------------------+
|
||
|
|
; K[2] ; 0.401 ; 0.000 ;
|
||
|
|
+-------+-------+-------------------+
|
||
|
|
|
||
|
|
|
||
|
|
-----------------------------------------
|
||
|
|
; Slow 1200mV 0C Model Recovery Summary ;
|
||
|
|
-----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------------
|
||
|
|
; Slow 1200mV 0C Model Removal Summary ;
|
||
|
|
----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
|
||
|
|
+-------+--------+---------------------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+--------+---------------------------------+
|
||
|
|
; K[2] ; -3.000 ; -10.435 ;
|
||
|
|
+-------+--------+---------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Setup: 'K[2]' ;
|
||
|
|
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; -0.219 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.148 ;
|
||
|
|
; -0.194 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.123 ;
|
||
|
|
; -0.193 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 1.122 ;
|
||
|
|
; 0.070 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.859 ;
|
||
|
|
; 0.070 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.859 ;
|
||
|
|
; 0.073 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.856 ;
|
||
|
|
; 0.159 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ;
|
||
|
|
; 0.159 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ;
|
||
|
|
; 0.159 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.770 ;
|
||
|
|
; 0.184 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.073 ; 0.745 ;
|
||
|
|
+--------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Slow 1200mV 0C Model Hold: 'K[2]' ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; 0.401 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ;
|
||
|
|
; 0.401 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ;
|
||
|
|
; 0.401 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.669 ;
|
||
|
|
; 0.416 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.684 ;
|
||
|
|
; 0.482 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.750 ;
|
||
|
|
; 0.484 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.752 ;
|
||
|
|
; 0.484 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.752 ;
|
||
|
|
; 0.716 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 0.984 ;
|
||
|
|
; 0.762 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 1.030 ;
|
||
|
|
; 0.782 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.073 ; 1.050 ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------------------
|
||
|
|
; Slow 1200mV 0C Model Metastability Summary ;
|
||
|
|
----------------------------------------------
|
||
|
|
No synchronizer chains to report.
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Setup Summary ;
|
||
|
|
+-------+-------+--------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+-------+--------------------+
|
||
|
|
; K[2] ; 0.404 ; 0.000 ;
|
||
|
|
+-------+-------+--------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Hold Summary ;
|
||
|
|
+-------+-------+-------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+-------+-------------------+
|
||
|
|
; K[2] ; 0.187 ; 0.000 ;
|
||
|
|
+-------+-------+-------------------+
|
||
|
|
|
||
|
|
|
||
|
|
-----------------------------------------
|
||
|
|
; Fast 1200mV 0C Model Recovery Summary ;
|
||
|
|
-----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------------
|
||
|
|
; Fast 1200mV 0C Model Removal Summary ;
|
||
|
|
----------------------------------------
|
||
|
|
No paths to report.
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
|
||
|
|
+-------+--------+---------------------------------+
|
||
|
|
; Clock ; Slack ; End Point TNS ;
|
||
|
|
+-------+--------+---------------------------------+
|
||
|
|
; K[2] ; -3.000 ; -8.315 ;
|
||
|
|
+-------+--------+---------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Setup: 'K[2]' ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; 0.404 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.547 ;
|
||
|
|
; 0.420 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.531 ;
|
||
|
|
; 0.422 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.529 ;
|
||
|
|
; 0.552 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.399 ;
|
||
|
|
; 0.553 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.398 ;
|
||
|
|
; 0.560 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.391 ;
|
||
|
|
; 0.592 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ;
|
||
|
|
; 0.592 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ;
|
||
|
|
; 0.592 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.359 ;
|
||
|
|
; 0.601 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 1.000 ; -0.036 ; 0.350 ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Fast 1200mV 0C Model Hold: 'K[2]' ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
; 0.187 ; LED_7seg_driver:inst|switcher[3] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ;
|
||
|
|
; 0.187 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ;
|
||
|
|
; 0.187 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.307 ;
|
||
|
|
; 0.194 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[0] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.314 ;
|
||
|
|
; 0.214 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[1] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.334 ;
|
||
|
|
; 0.215 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.335 ;
|
||
|
|
; 0.216 ; LED_7seg_driver:inst|switcher[0] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.336 ;
|
||
|
|
; 0.310 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[2] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.430 ;
|
||
|
|
; 0.337 ; LED_7seg_driver:inst|switcher[1] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.457 ;
|
||
|
|
; 0.348 ; LED_7seg_driver:inst|switcher[2] ; LED_7seg_driver:inst|switcher[3] ; K[2] ; K[2] ; 0.000 ; 0.036 ; 0.468 ;
|
||
|
|
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||
|
|
|
||
|
|
|
||
|
|
----------------------------------------------
|
||
|
|
; Fast 1200mV 0C Model Metastability Summary ;
|
||
|
|
----------------------------------------------
|
||
|
|
No synchronizer chains to report.
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------------+
|
||
|
|
; Multicorner Timing Analysis Summary ;
|
||
|
|
+------------------+--------+-------+----------+---------+---------------------+
|
||
|
|
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
|
||
|
|
+------------------+--------+-------+----------+---------+---------------------+
|
||
|
|
; Worst-case Slack ; -0.356 ; 0.187 ; N/A ; N/A ; -3.000 ;
|
||
|
|
; K[2] ; -0.356 ; 0.187 ; N/A ; N/A ; -3.000 ;
|
||
|
|
; Design-wide TNS ; -0.706 ; 0.0 ; 0.0 ; 0.0 ; -10.435 ;
|
||
|
|
; K[2] ; -0.706 ; 0.000 ; N/A ; N/A ; -10.435 ;
|
||
|
|
+------------------+--------+-------+----------+---------+---------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Board Trace Model Assignments ;
|
||
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||
|
|
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
||
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||
|
|
; HEX[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; HEX[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; HEX[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; HEX[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; HEX[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; HEX[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; HEX[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; HEX[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; SEG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; SEG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; SEG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; SEG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; SEG[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; SEG[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; SEG[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------+
|
||
|
|
; Input Transition Times ;
|
||
|
|
+-------------------------+--------------+-----------------+-----------------+
|
||
|
|
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||
|
|
+-------------------------+--------------+-----------------+-----------------+
|
||
|
|
; K[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||
|
|
; K[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||
|
|
; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||
|
|
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||
|
|
; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||
|
|
+-------------------------+--------------+-----------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ;
|
||
|
|
; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.33 V ; -0.00425 V ; 0.168 V ; 0.058 V ; 3.12e-09 s ; 2.87e-09 s ; Yes ; Yes ;
|
||
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ;
|
||
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ;
|
||
|
|
; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.33 V ; -0.00229 V ; 0.111 V ; 0.057 V ; 3.78e-09 s ; 3.5e-09 s ; Yes ; Yes ;
|
||
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ;
|
||
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
; HEX[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
|
||
|
|
; HEX[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; HEX[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||
|
|
; SEG[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ;
|
||
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
|
||
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------+
|
||
|
|
; Setup Transfers ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
; K[2] ; K[2] ; 10 ; 0 ; 0 ; 0 ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------+
|
||
|
|
; Hold Transfers ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
; K[2] ; K[2] ; 10 ; 0 ; 0 ; 0 ;
|
||
|
|
+------------+----------+----------+----------+----------+----------+
|
||
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||
|
|
|
||
|
|
|
||
|
|
---------------
|
||
|
|
; Report TCCS ;
|
||
|
|
---------------
|
||
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
||
|
|
|
||
|
|
|
||
|
|
---------------
|
||
|
|
; Report RSKM ;
|
||
|
|
---------------
|
||
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------+
|
||
|
|
; Unconstrained Paths Summary ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
; Property ; Setup ; Hold ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
; Illegal Clocks ; 0 ; 0 ;
|
||
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
||
|
|
; Unconstrained Input Ports ; 1 ; 1 ;
|
||
|
|
; Unconstrained Input Port Paths ; 1 ; 1 ;
|
||
|
|
; Unconstrained Output Ports ; 10 ; 10 ;
|
||
|
|
; Unconstrained Output Port Paths ; 41 ; 41 ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------+
|
||
|
|
; Clock Status Summary ;
|
||
|
|
+--------+-------+------+-------------+
|
||
|
|
; Target ; Clock ; Type ; Status ;
|
||
|
|
+--------+-------+------+-------------+
|
||
|
|
; K[2] ; K[2] ; Base ; Constrained ;
|
||
|
|
+--------+-------+------+-------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Input Ports ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; Input Port ; Comment ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; K[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Output Ports ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; Output Port ; Comment ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; HEX[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; HEX[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; HEX[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Input Ports ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; Input Port ; Comment ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; K[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Output Ports ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; Output Port ; Comment ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; HEX[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; HEX[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; HEX[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; SEG[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------+
|
||
|
|
; Timing Analyzer Messages ;
|
||
|
|
+--------------------------+
|
||
|
|
Info: *******************************************************************
|
||
|
|
Info: Running Quartus Prime Timing Analyzer
|
||
|
|
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||
|
|
Info: Processing started: Sat Apr 24 03:42:22 2021
|
||
|
|
Info: Command: quartus_sta template -c template
|
||
|
|
Info: qsta_default_script.tcl version: #1
|
||
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||
|
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||
|
|
Info (21077): Low junction temperature is 0 degrees C
|
||
|
|
Info (21077): High junction temperature is 85 degrees C
|
||
|
|
Critical Warning (332012): Synopsys Design Constraints File file not found: 'template.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||
|
|
Info (332105): Deriving Clocks
|
||
|
|
Info (332105): create_clock -period 1.000 -name K[2] K[2]
|
||
|
|
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
|
||
|
|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||
|
|
Info: Analyzing Slow 1200mV 85C Model
|
||
|
|
Critical Warning (332148): Timing requirements not met
|
||
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
|
||
|
|
Info (332146): Worst-case setup slack is -0.356
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -0.356 -0.706 K[2]
|
||
|
|
Info (332146): Worst-case hold slack is 0.453
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): 0.453 0.000 K[2]
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -3.000 -10.435 K[2]
|
||
|
|
Info: Analyzing Slow 1200mV 0C Model
|
||
|
|
Info (334003): Started post-fitting delay annotation
|
||
|
|
Info (334004): Delay annotation completed successfully
|
||
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
|
||
|
|
Critical Warning (332148): Timing requirements not met
|
||
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
|
||
|
|
Info (332146): Worst-case setup slack is -0.219
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -0.219 -0.412 K[2]
|
||
|
|
Info (332146): Worst-case hold slack is 0.401
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): 0.401 0.000 K[2]
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -3.000 -10.435 K[2]
|
||
|
|
Info: Analyzing Fast 1200mV 0C Model
|
||
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
|
||
|
|
Info (332146): Worst-case setup slack is 0.404
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): 0.404 0.000 K[2]
|
||
|
|
Info (332146): Worst-case hold slack is 0.187
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): 0.187 0.000 K[2]
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Critical Warning (332148): Timing requirements not met
|
||
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
|
||
|
|
Info (332146): Worst-case minimum pulse width slack is -3.000
|
||
|
|
Info (332119): Slack End Point TNS Clock
|
||
|
|
Info (332119): ========= =================== =====================
|
||
|
|
Info (332119): -3.000 -8.315 K[2]
|
||
|
|
Info (332102): Design is not fully constrained for setup requirements
|
||
|
|
Info (332102): Design is not fully constrained for hold requirements
|
||
|
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||
|
|
Info: Peak virtual memory: 444 megabytes
|
||
|
|
Info: Processing ended: Sat Apr 24 03:42:23 2021
|
||
|
|
Info: Elapsed time: 00:00:01
|
||
|
|
Info: Total CPU time (on all processors): 00:00:01
|
||
|
|
|
||
|
|
|