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26 lines
1.2 KiB
26 lines
1.2 KiB
4 years ago
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-- WARNING: Do NOT edit the input and output ports in this file in a text
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-- editor if you plan to continue editing the block that represents it in
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-- the Block Editor! File corruption is VERY likely to occur.
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-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- Generated by Quartus Prime Version 20.1 (Build Build 720 11/11/2020)
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-- Created on Sat Apr 24 03:39:58 2021
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FUNCTION 7seg_driver (D[3..0])
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RETURNS (SEG[6..0]);
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