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23 lines
698 B
23 lines
698 B
3 years ago
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subdesign 7seg_driver (D[3..0]: input = VCC; SEG[6..0]: output;)
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begin
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case d[] is
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when 0 => SEG[6..0] = b"0000001";
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when 1 => SEG[6..0] = b"1001111";
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when 2 => SEG[6..0] = b"0010010";
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when 3 => SEG[6..0] = b"0000110";
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when 4 => SEG[6..0] = b"1001100";
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when 5 => SEG[6..0] = b"0100100";
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when 6 => SEG[6..0] = b"0100000";
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when 7 => SEG[6..0] = b"0001111";
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when 8 => SEG[6..0] = b"0000000";
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when 9 => SEG[6..0] = b"0000100";
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when 10 => SEG[6..0] = b"0001000";
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when 11 => SEG[6..0] = b"1100000";
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when 12 => SEG[6..0] = b"0110001";
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when 13 => SEG[6..0] = b"1000010";
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when 14 => SEG[6..0] = b"0110000";
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when 15 => SEG[6..0] = b"0111000";
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when others => SEG[6..0] = VCC;
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end case;
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end;
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